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Descripción
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| We present a methodology for power estimation of nonfractional divider cores implemented in FPGAs. The methodolgy takes into account the divider structure and the signal statistics at the inputs: mean, variance, and autocorrelation. An analytical model is used for switching activity computation. The strong data dependency observed at the inputs of the divider basic elements is properly modelled in order to improve the model accuracy. The methodology is capable of obtaining fast and accurate estimates when compared to both, real on-board measurements and XPower. The mean relative error is less than 10%, with a maximum error of 22% when estimates are compared to on-board measurements and less than 11% when estimates are compared to low-level estimates provided by the commercial tool. divider are derived in order to enable signal propagation to the other components in the design. | |
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Internacional
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Si |
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Nombre congreso
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ACM/SIGDA Great Lakes Symposium on VLSI, GLSVLSI'11 |
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Tipo de participación
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960 |
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Lugar del congreso
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Lausana (Suiza) |
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Revisores
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Si |
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ISBN o ISSN
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978-1-4503-0667-6 |
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DOI
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Fecha inicio congreso
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02/05/2011 |
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Fecha fin congreso
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04/05/2011 |
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Desde la página
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313 |
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Hasta la página
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318 |
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Título de las actas
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Proceedings of the ACM/SIGDA Great Lakes Symposium on VLSI |