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Memorias de investigación
Communications at congresses:
Power Estimation of Dividers Implemented in FPGAs
Year:2011
Research Areas
  • Microelectronics
Information
Abstract
We present a methodology for power estimation of nonfractional divider cores implemented in FPGAs. The methodolgy takes into account the divider structure and the signal statistics at the inputs: mean, variance, and autocorrelation. An analytical model is used for switching activity computation. The strong data dependency observed at the inputs of the divider basic elements is properly modelled in order to improve the model accuracy. The methodology is capable of obtaining fast and accurate estimates when compared to both, real on-board measurements and XPower. The mean relative error is less than 10%, with a maximum error of 22% when estimates are compared to on-board measurements and less than 11% when estimates are compared to low-level estimates provided by the commercial tool. divider are derived in order to enable signal propagation to the other components in the design.
International
Si
Congress
ACM/SIGDA Great Lakes Symposium on VLSI, GLSVLSI'11
960
Place
Lausana (Suiza)
Reviewers
Si
ISBN/ISSN
978-1-4503-0667-6
Start Date
02/05/2011
End Date
04/05/2011
From page
313
To page
318
Proceedings of the ACM/SIGDA Great Lakes Symposium on VLSI
Participants
  • Autor: Ruzica Jevtic . (UPM)
  • Autor: Bojan Jovanovic (University of Nis)
  • Autor: Carlos Carreras Vaquer (UPM)
Research Group, Departaments and Institutes related
  • Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
  • Departamento: Ingeniería Electrónica
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