Observatorio de I+D+i UPM

Memorias de investigación
Research Publications in journals:
Customizing floating-point units for FPGAs: Area-performance-standard trade-offs
Year:2011
Research Areas
  • Microelectronics
Information
Abstract
Abstract The high integration density of current nanometer technologies allows the implementation of complex floating-point applications in a single FPGA. In this work the intrinsic complexity of floating-point operators is addressed targeting configurable devices and making design decisions providing the most suitable performance-standard compliance trade-offs. A set of floating-point libraries composed of adder/subtracter, multiplier, divisor, square root, exponential, logarithm and power function are presented. Each library has been designed taking into account special characteristics of current FPGAs, and with this purpose we have adapted the IEEE floating-point standard (software-oriented) to a custom FPGA-oriented format. Extended experimental results validate the design decisions made and prove the usefulness of reducing the format complexity.
International
Si
JCR
Si
Title
Microprocessors And Microsystems
ISBN
0141-9331
Impact factor JCR
0,545
Impact info
Volume
35
dx.doi.org/10.1016/j.micpro.2011.04.004
Journal number
6
From page
535
To page
546
Month
AGOSTO
Ranking
Participants
  • Autor: M. Luisa Lopez Vallejo (UPM)
Research Group, Departaments and Institutes related
  • Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
  • Departamento: Ingeniería Electrónica
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