Observatorio de I+D+i UPM

Memorias de investigación
Communications at congresses:
Suitability of artificial neural network for designing LoC circuits
Year:2011
Research Areas
  • Engineering
Information
Abstract
The simulation of complex LoC (Lab-on-a-Chip) devices is a process that requires solving computationally expensive partial di?eren- tial equations. An interesting alternative uses arti?cial neural networks for creating computationally feasible models based on MOR techniques. This paper proposes an approach that uses arti?cial neural networks for designing LoC components considering the arti?cial neural network topology as an isomorphism of the LoC device topology. The parameters of the trained neural networks are based on equations for modeling mi- cro uidic circuits, analogous to electronic circuits. The neural networks have been trained to behave like AND, OR, Inverter gates. The parame- ters of the trained neural networks represent the features of LoC devices that behave as the aforementioned gates. This would mean that LoC devices universally compute.
International
Si
Congress
International Work Conference in Artificial Neural Networks (IWANN)
960
Place
Reviewers
Si
ISBN/ISSN
Start Date
End Date
From page
To page
Participants
  • Autor: David Moreno
  • Autor: Sandra Maria Gomez Canaval (UPM)
  • Autor: Juan Bautista Castellanos Peñuela (UPM)
Research Group, Departaments and Institutes related
  • Creador: Grupo de Investigación: Grupo de Computación Natural
  • Departamento: Inteligencia Artificial
  • Departamento: Lenguajes, Proyectos y Sistemas Informáticos
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