Observatorio de I+D+i UPM

Memorias de investigación
Communications at congresses:
Cycle-Accurate Configuration Layer Model for Xilinx Virtex FPGAs
Year:2011
Research Areas
  • Microelectronics
Information
Abstract
A cycle-accurate VHDL simulation model for the Xilinx Virtex-4 (and on) FPGA Configuration Layer is presented. This model allows for simulating configuration memory SEU injection and correction dynamics, as well as control logic SEFI recovery, with independence from Application Layer. Scrubber designs can be efficiently simulated, together with one or more instances of this model, prior to hardware implementation. This significantly improves design observability and simplifies the validation of such designs.
International
Si
Congress
RADECS
960
Place
Sevilla, España
Reviewers
Si
ISBN/ISSN
0379-6566
10.1109/RADECS.2011.6131394
Start Date
27/09/2011
End Date
30/09/2011
From page
182
To page
185
12th European Conference on Radiation and Its Effects on Components and Systems (RADECS), 2011
Participants
  • Autor: Ignacio Herrera Alzu
  • Autor: M. Luisa Lopez Vallejo (UPM)
Research Group, Departaments and Institutes related
  • Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
  • Departamento: Ingeniería Electrónica
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