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Memorias de investigación
Communications at congresses:
Suitability of Artificial Neural Networks for Designing LoC Circuits
Year:2011
Research Areas
  • Information technology and adata processing
Information
Abstract
he simulation of complex LoC (Lab-on-a-Chip) devices is a process that requires solving computationally expensive partial differential equations. An interesting alternative uses artificial neural networks for creating computationally feasible models based on MOR techniques. This paper proposes an approach that uses artificial neural networks for designing LoC components considering the artificial neural network topology as an isomorphism of the LoC device topology. The parameters of the trained neural networks are based on equations for modeling microfluidic circuits, analogous to electronic circuits. The neural networks have been trained to behave like AND, OR, Inverter gates. The parameters of the trained neural networks represent the features of LoC devices that behave as the aforementioned gates. This would mean that LoC devices universally compute.
International
Si
Congress
11th international conference on Artificial neural networks conference on Advances in computational intelligence
960
Place
Torremolinos-Málaga, Spain, June 8-10, 2011,
Reviewers
Si
ISBN/ISSN
978-3-642-21497-4
Start Date
08/06/2011
End Date
10/06/2011
From page
307
To page
314
Proceedings IWANN'11 Proceedings of the 11th international conference on Artificial neural networks conference on Advances in computational intelligence - Volume Part I
Participants
  • Autor: Sandra Maria Gomez Canaval (UPM)
  • Autor: Juan Bautista Castellanos Peñuela (UPM)
Research Group, Departaments and Institutes related
  • Creador: Grupo de Investigación: Grupo de Computación Natural
  • Departamento: Lenguajes, Proyectos y Sistemas Informáticos
  • Departamento: Inteligencia Artificial
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Cofinanciación del MINECO en el marco del Programa INNCIDE 2011 (OTR-2011-0236)
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