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Descripción
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| When estimating the dynamic power consumption of DSP datapaths, it is crucial to accurately calculate switching activity produced inside the design. For accurate switching activity calculation the existence of an appropriate data signal model is essential. This paper presents a triple-bit type (TBT) signal model which is used to represent bit-level switching activity at the output of multipliers. The model depends on wordlevel signal statistics and the number of multiplied input signals. For the sake of comparison with the standard dual-bit type (DBT) signal model, both models (TBT and DBT) are applied to the high-level power estimation of three reference designs implemented in FPGA. Calculated with respect to the measured power, the relative errors of here presented TBT model are four to five times smaller than the errors of the DBT model. | |
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Internacional
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Si |
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Nombre congreso
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4th Small Systems Simulation Symposium, SSSS'12 |
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Tipo de participación
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960 |
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Lugar del congreso
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Nis (Serbia) |
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Revisores
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Si |
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ISBN o ISSN
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978-86-6125-059-0 |
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DOI
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Fecha inicio congreso
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12/02/2012 |
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Fecha fin congreso
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14/02/2012 |
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Desde la página
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62 |
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Hasta la página
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66 |
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Título de las actas
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Proceedings of the 4th Small Systems Simulation Symposium |