|
Descripción
|
|
|---|---|
| This paper presents an implementation of a frequency agility algorithm for a CWFM radar, which is able to process samples in excess of 60MHz, increasing SNR in exchange of increased bandwidth or decreased distance resolution. This implementation has been realized on a Virtex5 FPGA using low cost memory chips. An experimental approach has allowed to determine the maximum sampling frequency that our implementation allows as-is, but higher speed memory chips may be used with the same HDL code, thus allowing faster sampling rates. | |
|
Internacional
|
No |
|
Nombre congreso
|
XXVIII Simposium Nacional de la Unión Científica Internacional de Radio. 2013 |
|
Tipo de participación
|
960 |
|
Lugar del congreso
|
Santiago de Compostela |
|
Revisores
|
Si |
|
ISBN o ISSN
|
978-84-941537-1-6 |
|
DOI
|
|
|
Fecha inicio congreso
|
11/09/2013 |
|
Fecha fin congreso
|
13/09/2013 |
|
Desde la página
|
95 |
|
Hasta la página
|
95 |
|
Título de las actas
|
Libro de Resúmenes y CD-ROM de Actas del Simposium |