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Descripción
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| Validation of a system design enables to discover specification errors before it is implemented (or tested), thus hopefully reducing the development cost and time. The Unified Modelling Language (UML) is becoming widely accepted for the early specification and analysis of requirements for safety-critical systems, although a better balance between UML?s undisputed flexibility, and a precise unambiguous semantics, is needed. In this paper we introduce UMerL, a tool that is capable of executing and formally verifying UML diagrams (namely, UML state machine, class and object diagrams) by means of a translation of its behavioural information into Erlang. The use of the tool is illustrated with an example in embedded software design. | |
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Internacional
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Si |
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Nombre congreso
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Software Engineering and Formal Methods |
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Tipo de participación
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960 |
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Lugar del congreso
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Grenoble, Francia |
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Revisores
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Si |
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ISBN o ISSN
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978-3-319-10431-7 |
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DOI
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Fecha inicio congreso
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01/09/2014 |
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Fecha fin congreso
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05/09/2014 |
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Desde la página
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284 |
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Hasta la página
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289 |
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Título de las actas
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Software Engineering and Formal Methods |