Observatorio de I+D+i UPM

Memorias de investigación
Communications at congresses:
A Dual-Layer Fault Manager for Systems based on Xilinx Virtex FPGAs
Year:2015
Research Areas
  • Design of electronic systems with digital configurable circuits (fpga, pld amd others),
  • Tools of design of integrate circuits
Information
Abstract
?Systems based on Xilinx Virtex series FPGAs can benefit, compared to traditional rad-hard technologies, from high performance, high logic density and dynamic reconfiguration capability. However, the underlying SRAM technology is sensitive to ionizing radiation, which can induce faults that must be managed to improve system?s dependability. This paper proposes a Dual-Layer Fault Manager concept, which aims at managing both configuration and application faults, dynamically balancing redundancy level, dependability and functionality. This concept has been prototyped and its initial test results are discussed.
International
Si
Congress
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2015 IEEE International Symposium on
960
Place
Amherst, MA, EEUU
Reviewers
Si
ISBN/ISSN
978-1-4799-8606-4
Start Date
12/10/2015
End Date
14/10/2015
From page
72
To page
75
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2015 IEEE International Symposium on
Participants
  • Autor: M. Luisa Lopez Vallejo (UPM)
Research Group, Departaments and Institutes related
  • Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
  • Departamento: Ingeniería Electrónica
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