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Descripción
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| This work presents SAEDE (Statistically-Aided Electronic Design Environment), a framework targeted to perform advanced statistical analysis within an ASIC design workflow, linking together circuit performance with technological parameters. A driving example, the design of a 10-stage delay line, is conducted. The study goals are two-fold: extract a circuit performance metric, the spread of the stage-delay, and determine its most sensitive BSIM4 transistor parameters. To achieve these goals, two statistical tools, new to ASIC design work-flow, have been used: Skew-Normal inference and BAHSIC feature selection. Consistent results are obtained, relating BSIM4 parameters to circuit performance impossible to grasp by analytical terms. | |
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Internacional
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Si |
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Nombre congreso
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Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2016 13th International Conference on |
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Tipo de participación
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960 |
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Lugar del congreso
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Lisboa, Portugal |
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Revisores
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Si |
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ISBN o ISSN
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978-1-5090-0490-4 |
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DOI
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10.1109/SMACD.2016.7520734 |
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Fecha inicio congreso
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27/06/2016 |
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Fecha fin congreso
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30/06/2016 |
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Desde la página
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1 |
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Hasta la página
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4 |
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Título de las actas
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Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2016 13th International Conference on |