Communications at congresses:
Evaluating High-Level Synthesis Techniques for Scalable Hardware-Accelerated Computing
Evaluating High-Level Synthesis Techniques for Scalable Hardware-Accelerated Computing
Year:2017
Research Areas
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Electric engineers, electronic and automatic (eil)
Information
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Abstract
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International
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Si |
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Congress
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Design of Circuits and Integrated Systems (DCIS 2017) |
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960 |
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Place
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Barcelona (Spain) |
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Reviewers
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Si |
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ISBN/ISSN
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000-0-0000-0000-0 |
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Start Date
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22/11/2017 |
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End Date
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24/11/2017 |
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From page
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1 |
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To page
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5 |
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Proceedings of Design of Circuits and Integrated Systems (DCIS 2017) |
Participants
- Autor: Alfonso Rodriguez Medina (UPM)
- Autor: Eduardo de la Torre Arnanz (UPM)
- Autor: Teresa Riesgo Alcaide (UPM)
Research Group, Departaments and Institutes related
- Creador: Grupo de Investigación: Electrónica Industrial
- Departamento: Automática, Ingeniería Eléctrica y Electrónica e Informática Industrial
S2i 2019 Observatorio de investigación @ UPM con la colaboración del Consejo Social UPM
Cofinanciación del MINECO en el marco del Programa INNPACTO (IPT-020000-2010-22)