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Memorias de investigación
Ponencias en congresos:
Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA Designs
Año:2018
Áreas de investigación
  • Diseño de circuitos integrados de circuitería reconfigurable
Datos
Descripción
Traditional FPGA design workflow requires the complete system in order to perform timing characterization. However, high-performance digital systems implementing scientific applications frequently occupy a large area and are suitably developed following a latency insensitive design approach to achieve multi-level parallelism. The produced circuits are composed of several deeply pipelined specialized computational macroblocks and try to maximize both the operating frequency and the usage of FPGA device resources to full capacity. These goals are most appropriately attainable through a decentralized control strategy and the optimization of performance for individual blocks independently from each other. This work proposes a synthesizable virtual wrapper architecture which does not add any functionality but simulates complete system conditions for the timing characterization of individual blocks using standard low-level synthesis tools. It further presents a high-level tool to generate both the computational blocks and the wrapper from a functional specification in C language, and shows that large blocks with inputs and outputs exceeding the available number of FPGA pins can be automatically generated and characterized. In particular, results for the blocks generated for a real computational fluid dynamics application are provided.
Internacional
Si
Nombre congreso
28th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS'18
Tipo de participación
960
Lugar del congreso
Platja D'Aro, Girona (España)
Revisores
Si
ISBN o ISSN
978-1-5386-6365-3
DOI
Fecha inicio congreso
02/07/2018
Fecha fin congreso
04/07/2018
Desde la página
7
Hasta la página
12
Título de las actas
Proceedings of the 28th International Symposium on Power and Timing Modeling, Optimization and Simulation
Esta actividad pertenece a memorias de investigación
Participantes
  • Autor: Roberto Sierra Cabrera (UPM)
  • Autor: Carlos Carreras Vaquer (UPM)
  • Autor: Gabriel Caffarena Fernández (Universidad San Pablo CEU)
Grupos de investigación, Departamentos, Centros e Institutos de I+D+i relacionados
  • Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
  • Centro o Instituto I+D+i: Centro de I+d+i en Procesado de la Información y Telecomunicaciones
  • Departamento: Ingeniería Electrónica
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