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Descripción
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| Currently, the evolutionary computing techniques are increasingly used in different fields, such as optimization, machine learning, and others. The starting point of the investigation is a set of optimization tools based on these techniques and one of them is called evolutionary grammar. It is an evolutionary technique derived from genetic algorithms and used to generate programs automatically in any type of language. The present work is focused on the design and evaluation of hardware acceleration technique through PSoC, for the execution of evolutionary grammar. For this, a ZYNQ development platform is used, in which the logical part is used to implement factory modules and independents hardware blocks made up of a soft-processor, memory BRAM, and a CORDIC module developed to perform arithmetic operations. The processing part is used for the execution of the algorithm. Throughout the development, the procedures and techniques used for hardware and software design are specified, and the viability of the implementation is analyzed considering the comparison of the algorithm execution times in Java versus the execution times in Hardware. | |
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Internacional
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Si |
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Nombre congreso
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Italian Workshop on Artificial Life and Evolutionary Computation, WIVACE2019 |
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Tipo de participación
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960 |
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Lugar del congreso
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Rende, Italy |
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Revisores
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Si |
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ISBN o ISSN
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978-3-030-45015-1 |
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DOI
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10.1007/978-3-030-45016-8 |
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Fecha inicio congreso
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18/09/2019 |
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Fecha fin congreso
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20/09/2019 |
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Desde la página
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100 |
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Hasta la página
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112 |
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Título de las actas
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Artificial Life and Evolutionary Computation 14th Italian Workshop, WIVACE 2019, Rende, Italy, September 18?20, 2019, Revised Selected Papers |