Memorias de investigación
Artículos en revistas:
Scalable Hardware-Based On-Board Processing for Run-Time Adaptive Lossless Hyperspectral Compression
Año:2019
Áreas de investigación
  • Ingeniería eléctrica, electrónica y automática
Datos
Descripción
Hyperspectral data processing is a computationally intensive task that is usually performed in high-performance computing clusters. However, in remote sensing scenarios, where communications are expensive, a compression stage is required at the edge of data acquisition before transmitting information to ground stations for further processing. Moreover, hyperspectral image compressors need to meet minimum performance and energy-efficiency levels to cope with the real-time requirements imposed by the sensors and the available power budget. Hence, they are usually implemented as dedicated hardware accelerators in expensive space-grade electronic devices. In recent years though, these devices have started to coexist with low-cost commercial alternatives in which unconventional techniques, such as run-time hardware reconfiguration are evaluated within research-oriented space missions (e.g., CubeSats). In this paper, a run-time reconfigurable implementation of a low-complexity lossless hyperspectral compressor (i.e., CCSDS 123) on a commercial off-the-shelf device is presented. The proposed approach leverages an FPGA-based on-board processing architecture with a data-parallel execution model to transparently manage a configurable number of resource-efficient hardware cores, dynamically adapting both throughput and energy efficiency. The experimental results show that this solution is competitive when compared with the current state-of-the-art hyperspectral compressors and that the impact of the parallelization scheme on the compression rate is acceptable when considering the improvements in terms of performance and energy consumption. Moreover, scalability tests prove that run-time adaptation of the compression throughput and energy efficiency can be achieved by modifying the number of hardware accelerators, a feature that can be useful in space scenarios, where requirements change over time (e.g., communication bandwidth or power budget).
Internacional
Si
JCR del ISI
Si
Título de la revista
IEEE ACCESS
ISSN
2169-3536
Factor de impacto JCR
Información de impacto
Volumen
7
DOI
10.1109/ACCESS.2019.2892308
Número de revista
Desde la página
10644
Hasta la página
10652
Mes
SIN MES
Ranking
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Participantes
Grupos de investigación, Departamentos, Centros e Institutos de I+D+i relacionados
  • Creador: Centro o Instituto I+D+i: Centro de Electrónica Industrial. CEI
  • Departamento: Automática, Ingeniería Eléctrica y Electrónica e Informática Industrial