Observatorio de I+D+i UPM

Memorias de investigación
Book chapters:
An FFT/IFFT design versus Altera and Xilinx cores
Research Areas
  • Processing and signal analysis
In this paper, a portable hardware design implementing a Fast Fourier Transform oriented to its reusability as a core is presented. The module has been developed using radix-2 Decimation-In-Time algorithm. Structural modeling is implemented using VHDL to describe, simulate and perform the design. The module is portable among different EDA tools and technology independent. It has been synthesized with Quartus II from Altera and ISE from Xilinx. The detailed performance results are presented, as well as a comparison between these and the results provided by Altera and Xilinx FFT IP cores. These show that the proposed design produces better results in the use of physical resources but worsens throughput when compared against the commercial ones. Besides, the IP core from Xilinx shows better throughput than Alteras’s but at a higher implementation cost.
Book Edition
Book Publishing
Book title
ReConFig’08. 2008 International Conference on Reconfigurable Computing and FPGAs
From page
To page
  • Autor: Coral González Concejero (UPM)
  • Autor: Agustin Alvarez Marquina (UPM)
  • Autor: M. Elvira Martinez de Icaya Gomez (UPM)
  • Autor: M. Victoria Rodellar Biarge (UPM)
  • Autor: Pedro Gomez Vilda (UPM)
Research Group, Departaments and Institutes related
  • Creador: Grupo de Investigación: Informática Aplicada al Procesado de Señal e Imagen
  • Departamento: Arquitectura y Tecnología de Sistemas Informáticos
  • Departamento: Arquitectura y Tecnología de Computadores (E.U. Informática)
S2i 2020 Observatorio de investigación @ UPM con la colaboración del Consejo Social UPM
Cofinanciación del MINECO en el marco del Programa INNCIDE 2011 (OTR-2011-0236)
Cofinanciación del MINECO en el marco del Programa INNPACTO (IPT-020000-2010-22)