Observatorio de I+D+i UPM

Memorias de investigación
Book chapters:
An FFT/IFFT design versus Altera and Xilinx cores
Year:2008
Research Areas
  • Processing and signal analysis
Information
Abstract
In this paper, a portable hardware design implementing a Fast Fourier Transform oriented to its reusability as a core is presented. The module has been developed using radix-2 Decimation-In-Time algorithm. Structural modeling is implemented using VHDL to describe, simulate and perform the design. The module is portable among different EDA tools and technology independent. It has been synthesized with Quartus II from Altera and ISE from Xilinx. The detailed performance results are presented, as well as a comparison between these and the results provided by Altera and Xilinx FFT IP cores. These show that the proposed design produces better results in the use of physical resources but worsens throughput when compared against the commercial ones. Besides, the IP core from Xilinx shows better throughput than Alteras’s but at a higher implementation cost.
International
Si
Book Edition
0
Book Publishing
ISBN
978-0-7695-3474-9
Series
Book title
ReConFig’08. 2008 International Conference on Reconfigurable Computing and FPGAs
From page
337
To page
342
Participants
  • Autor: Coral González Concejero (UPM)
  • Autor: Agustin Alvarez Marquina (UPM)
  • Autor: M. Elvira Martinez de Icaya Gomez (UPM)
  • Autor: M. Victoria Rodellar Biarge (UPM)
  • Autor: Pedro Gomez Vilda (UPM)
Research Group, Departaments and Institutes related
  • Creador: Grupo de Investigación: Informática Aplicada al Procesado de Señal e Imagen
  • Departamento: Arquitectura y Tecnología de Sistemas Informáticos
  • Departamento: Arquitectura y Tecnología de Computadores (E.U. Informática)
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