Memorias de investigación
Capítulo de libro:
Pipeline-Based Power Reduction in FPGA Applications
Año:2008
Áreas de investigación
  • Procesado y análisis de la señal
Datos
Descripción
In this paper, a portable hardware design implementing a Fast Fourier Transform oriented to its reusability as a core is presented. The module has been developed using radix-2 Decimation-In-Time algorithm. Structural modeling is implemented using VHDL to describe, simulate and perform the design. The module is portable among different EDA tools and technology independent. It has been synthesized with Quartus II from Altera and ISE from Xilinx. The detailed performance results are presented, as well as a comparison between these and the results provided by Altera and Xilinx FFT IP cores. These show that the proposed design produces better results in the use of physical resources but worsens throughput when compared against the commercial ones. Besides, the IP core from Xilinx shows better throughput than Alteras’s but at a higher implementation cost.
Internacional
Si
DOI
Edición del Libro
0
Editorial del Libro
ISBN
978-84-612-2376-3
Serie
Título del Libro
2008, 4th Southern Conference on Programmable Logic
Desde página
43
Hasta página
47
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Participantes
Grupos de investigación, Departamentos, Centros e Institutos de I+D+i relacionados
  • Creador: Grupo de Investigación: Informática Aplicada al Procesado de Señal e Imagen
  • Departamento: Arquitectura y Tecnología de Sistemas Informáticos
  • Departamento: Arquitectura y Tecnología de Computadores (E.U. Informática)