Memorias de investigación
Ponencias en congresos:
Analytical High-level Power model for LUT-based Components
Año:2008
Áreas de investigación
  • Industria electrónica
Datos
Descripción
This paper presents an extended high-level model for logic power estimation of multipliers and adders implemented in FPGAs in the presence of glitching and correlation. The model is based on an analytical computation of the switching activity produced in the component and the FPGA implementation details of the component structure. It is extended to consider operands of different word-lengths, both zero-mean and non-zero mean signals, and the glitching produced inside the component, taking into account the sign nature of the autocorrelation coefficients of the components¿ inputs. The number of simulations needed for the model characterization is extremely small and can be reduced to only two. As the final power model is analytical, it is capable of providing power estimates in miliseconds. The results show that the mean relative error is within 10% of low-level power estimates given by the XPower tool.
Internacional
Si
Nombre congreso
18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS'08
Tipo de participación
960
Lugar del congreso
Lisboa (Portugal)
Revisores
Si
ISBN o ISSN
DOI
Fecha inicio congreso
10/09/2008
Fecha fin congreso
12/09/2008
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0
Hasta la página
0
Título de las actas
Proceedings of the 18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS'08
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Participantes
Grupos de investigación, Departamentos, Centros e Institutos de I+D+i relacionados
  • Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
  • Departamento: Ingeniería Electrónica