Observatorio de I+D+i UPM

Memorias de investigación
Combined Word-Length Allocation and High-Level Synthesis of Digital Signal Processing Circuits.
Áreas de investigación
  • Industria electrónica
This work is focused on the synthesis of Digital Signal Processing (DSP) circuits using specific hardware architectures. Due to its complexity, the design process has been subdivided into separate tasks, thus hindering the global optimization of the resulting systems. The author proposes the study of the combination of two major design tasks, Word-Length Allocation (WLA) and High-Level Synthesis (HLS), aiming at the optimization of DSP implementations using modern Field Programmable Gate Array devices (FPGAs). A multiple word-length approach (MWL) is adopted since it leads to highly optimized implementations. MWL implies the customization of the word-lengths of the signals of an algorithm. This complicates the design, since the number possible assignations between algorithm operations and hardware resources becomes very high. Moreover, this work also considers the use of heterogeneous FPGAs where there are several types of resources: configurable logic-based blocks (LUT-based) and specialized embedded resources. All these issues are addressed in this work and several automatic design techniques are proposed. The contributions of the Thesis cover the fields of WLA, HLS using FPGAs, and the combined application of WLA and HLS for implementation in FPGAs.
Tipo de Tesis
Sobresaliente cum laude
Esta actividad pertenece a memorias de investigación
  • Director: Octavio Nieto-Taladriz Garcia (UPM)
  • Director: Carlos Carreras Vaquer (UPM)
  • Autor: Gabriel Caffarena Fernandez (UPM)
Grupos de investigación, Departamentos, Centros e Institutos de I+D+i relacionados
  • Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
  • Departamento: Ingeniería Electrónica
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