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Memorias de investigación
Communications at congresses:
A Practical Method for Testing High-speed Networking Hardware Architectures
Year:2009
Research Areas
  • Electronics engineering
Information
Abstract
This paper deals with the key issues encountered in testing during the development of high-speed networking hardware systems by documenting a practical method for "real-life like" testing. The proposed method is empowered by modern and commonly available Field Programmable Gate Array (FPGA) technology. Innovative application of standard FPGA blocks in combination with reconfigurability are used as a back-bone of the method. A detailed elaboration of the method is given so as to serve as a general reference. The method is fully characterised and compared to alternatives through a case study proving it to be the most efficient and effective one at a reasonable cost.
International
Si
Congress
960
Place
Reviewers
ISBN/ISSN
Start Date
End Date
From page
To page
Participants
  • Autor: Vukasin Pejovic . (UPM)
  • Autor: Slobodan Bojanic Antonijevic (UPM)
  • Autor: Carlos Carreras Vaquer (UPM)
Research Group, Departaments and Institutes related
  • Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
  • Departamento: Ingeniería Electrónica
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