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Descripción
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| Process variation in future technologies can cause severe performance degradation since different parts of the shared Register File (RF) in VLIW processors may operate at various speeds. In this paper we present a complete approach that handles speed variability of the RF proposing different compiletime and run-time design alternatives. (Proceedings pp.121-124). | |
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Internacional
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Si |
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Nombre congreso
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IEEE International Symposium on Circuits and Systems, ISCAS'07 |
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Tipo de participación
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960 |
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Lugar del congreso
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New Orleans (USA) |
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Revisores
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Si |
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ISBN o ISSN
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1-4244-0921-7 |
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DOI
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Fecha inicio congreso
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27/05/2007 |
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Fecha fin congreso
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30/05/2007 |
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