Descripción
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In this paper, the interdependency of the design tasks of fixed-point optimization and architectural synthesis is analyzed, aiming at FPGA implementations. Fixed-point arithmetic is widely adopted for low-cost FPGA implementations of DSP algorithm. Despite his success, there are still many open issues regarding the automatic synthesis of fixed-point circuits. Normally, fixed-point optimization is performed without considering any architectural issues or assuming a fully parallel implementation. Thus, any architectural optimization made after may produce non-optimal results. The effect of using different fixed-point optimization methods on the final architecture is studied. Several methods to perform fixed-point optimization, architectural synthesis, and the combination of both, are presented. The analysis considers both LUT-based resources and DSP blocks. The results yield that when the architectural model used during the two design tasks, does not match, then, it is not necessary to perform a thorough -- and time-consuming -- fixed-point optimization (i.e. simulated annealing). Also, the combined synthesis techniques produces area reductions up to 20\%. | |
Internacional
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No |
Nombre congreso
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XI Jornadas de Computación Reconfigurable y Aplicaciones, JCRA'11 |
Tipo de participación
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960 |
Lugar del congreso
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Tenerife (España= |
Revisores
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Si |
ISBN o ISSN
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978-84-614881-4-8 |
DOI
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Fecha inicio congreso
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07/09/2011 |
Fecha fin congreso
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09/09/2011 |
Desde la página
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269 |
Hasta la página
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278 |
Título de las actas
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Actas de las XI Jornadas de Computación Reconfigurable y Aplicaciones |