Observatorio de I+D+i UPM

Memorias de investigación
Proyecto de I+D+i:
FASTCUDA: Open Source FPGA Accelerator & Hardware-Software Codesign Toolset for CUDA Kernels
Áreas de investigación

Europe has a strong leadership in the domains of intelligent telecommunications, multimedia, and automotive systems. However, the exponential increase in complexity of intelligent systems threatens the European competitiveness.

In order to solve today’s challenges of high-complex design for embedded electronic systems, a number of approaches have been tried. Hardware-software codesign is the first big step and an essential enabling technology towards this end. Electronic System Level (ESL) design methodologies is the next big step which addresses the complexity problem by elevating design to a higher level of abstraction, resulting in a more predictable and productive design process. Finally, parallel hardware platforms such as Graphical Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs) are becoming very popular within PC-based heterogeneous systems for speeding up numerous compute-intensive applications.

FASTCUDA is a platform that provides the necessary software tools, hardware architecture, and design methodology to efficiently adapt CUDA (a parallel-computing architecture and API which is driven by the GPU industry, with wide adoption in many diverse fields ranging from molecular dynamics, to computational chemistry, to image or video processing, etc.) into a new FPGA design flow. With FASTCUDA, the CUDA kernels of a CUDA-based application are automatically partitioned into two groups: some are compiled and executed in parallel software, while the remaining are synthesized and implemented in hardware. A modern low power FPGA provides the processing power (via hundreds of embedded micro-CPUs) and the logic capacity for the implementation of all the software and the hardware components.

In particular, we plan to join the numerous on-going efforts in industry and academia to create a unified best-practice, industrial-quality, open-source framework that will enable an easier transition from research results to industrial exploitation.

Tipo de proyecto
Proyectos y convenios en convocatorias públicas competitivas
Entidad financiadora
Comisión Europea
Nacionalidad Entidad
Tamaño de la entidad
Fecha concesión
Esta actividad pertenece a memorias de investigación
  • Director: Teresa Riesgo Alcaide (UPM)
  • Participante: Eduardo de la Torre Arnanz (UPM)
  • Participante: Jorge Portilla Berrueco (UPM)
  • Participante: Felix Moreno Lizana (UPM)
  • Participante: Yago Torroja Fungairiño (UPM)
  • Participante: Jose Andres Otero Marnotes (UPM)
  • Participante: Ruben Salvador Perea (UPM)
Grupos de investigación, Departamentos, Centros e Institutos de I+D+i relacionados
  • Creador: No seleccionado
  • Grupo de Investigación: Electrónica Industrial
  • Centro o Instituto I+D+i: Centro de Electrónica Industrial. CEI
  • Departamento: Automática, Ingeniería Electrónica e Informática Industrial
S2i 2023 Observatorio de investigación @ UPM con la colaboración del Consejo Social UPM
Cofinanciación del MINECO en el marco del Programa INNCIDE 2011 (OTR-2011-0236)
Cofinanciación del MINECO en el marco del Programa INNPACTO (IPT-020000-2010-22)