Artículos en revistas:
Customizing floating-point units for FPGAs: Area-performance-standard trade-offs
Año:2011
Áreas de investigación
- Microelectrónica
Datos
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Descripción
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| Abstract The high integration density of current nanometer technologies allows the implementation of complex floating-point applications in a single FPGA. In this work the intrinsic complexity of floating-point operators is addressed targeting configurable devices and making design decisions providing the most suitable performance-standard compliance trade-offs. A set of floating-point libraries composed of adder/subtracter, multiplier, divisor, square root, exponential, logarithm and power function are presented. Each library has been designed taking into account special characteristics of current FPGAs, and with this purpose we have adapted the IEEE floating-point standard (software-oriented) to a custom FPGA-oriented format. Extended experimental results validate the design decisions made and prove the usefulness of reducing the format complexity. | |
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Internacional
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Si |
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JCR del ISI
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Si |
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Título de la revista
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Microprocessors And Microsystems |
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ISSN
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0141-9331 |
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Factor de impacto JCR
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0,545 |
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Información de impacto
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Volumen
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35 |
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DOI
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dx.doi.org/10.1016/j.micpro.2011.04.004 |
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Número de revista
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6 |
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Desde la página
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535 |
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Hasta la página
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546 |
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Mes
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AGOSTO |
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Ranking
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Participantes
- Autor: M. Luisa Lopez Vallejo UPM
Grupos de investigación, Departamentos, Centros e Institutos de I+D+i relacionados
- Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
- Departamento: Ingeniería Electrónica