Observatorio de I+D+i UPM

Descripción
SRAM-based FPGAs are sensitive to radiation effects. Soft errors can appear and accumulate, potentially defeating mitigation strategies deployed at the Application Layer. Therefore, Configuration Memory scrubbing is required to improve radiation tolerance of such FP- GAs in space applications. Virtex FPGAs allow runtime scrubbing by means of dynamic partial reconfiguration. Even with scrubbing, intra- FPGA TMR systems are subjected to common-mode errors affecting more than one design domain. This is solved in inter-FPGA TMR sys- tems at the expense of a higher cost, power and mass. In this context, a self-reference scrubber for device-level TMR system based on Xilinx Virtex FPGAs is presented. This scrubber allows for a fast SEU/MBU detection and correction by peer frame comparison without needing to access a golden configuration memory.
Internacional	Si
Nombre congreso	INTEGRATED CIRCUIT AND SYSTEM DESIGN. POWER AND TIMING MODELING, OPTIMIZATION, AND SIMULATION (PATMOS 2012)
Tipo de participación	960
Lugar del congreso	Madrid, España
Revisores	Si
ISBN o ISSN	978-3-642-24153-6
DOI
Fecha inicio congreso	26/09/2011
Fecha fin congreso	29/09/2011
Desde la página	133
Hasta la página	142
Título de las actas	Lecture Notes in Computer Science, 2011, Volume 6951/2011

Esta actividad pertenece a memorias de investigación

• Autor: M. Luisa Lopez Vallejo (UPM)

• Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
• Departamento: Ingeniería Electrónica