Descripción
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SRAM-based FPGAs are sensitive to radiation effects. Soft errors can appear and accumulate, potentially defeating mitigation strategies deployed at the Application Layer. Therefore, Configuration Memory scrubbing is required to improve radiation tolerance of such FP- GAs in space applications. Virtex FPGAs allow runtime scrubbing by means of dynamic partial reconfiguration. Even with scrubbing, intra- FPGA TMR systems are subjected to common-mode errors affecting more than one design domain. This is solved in inter-FPGA TMR sys- tems at the expense of a higher cost, power and mass. In this context, a self-reference scrubber for device-level TMR system based on Xilinx Virtex FPGAs is presented. This scrubber allows for a fast SEU/MBU detection and correction by peer frame comparison without needing to access a golden configuration memory. | |
Internacional
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Si |
Nombre congreso
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INTEGRATED CIRCUIT AND SYSTEM DESIGN. POWER AND TIMING MODELING, OPTIMIZATION, AND SIMULATION (PATMOS 2012) |
Tipo de participación
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960 |
Lugar del congreso
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Madrid, España |
Revisores
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Si |
ISBN o ISSN
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978-3-642-24153-6 |
DOI
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Fecha inicio congreso
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26/09/2011 |
Fecha fin congreso
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29/09/2011 |
Desde la página
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133 |
Hasta la página
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142 |
Título de las actas
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Lecture Notes in Computer Science, 2011, Volume 6951/2011 |