Memorias de investigación
Communications at congresses:
Design and Implementation of Floating-Point FFT Architectures for FPGA Devices
Year:2012

Research Areas
  • Design of integrate circuits to reshape circuitry

Information
Abstract
The integration degree achieved by nanometer technologies allows the implementation of complex applications in current FPGAs. This is the case of computations that use floating-point arithmetic, characterized by requiring large amounts of resources and long design times. One of the most used algorithms is the FFT, so an implementation of this algorithm in floating-point format is necessary to improve implemented systems and to make more powerful the new designs that will be developed in the next years. The optimization of this implementation is very useful when these devices allow the processing of long signals, at that moment floating point outperforms fixed point format. In this work three different architectures are presented and characterized in terms of resources and performance. Finally each architecture is recommended for different types of applications depending on their particular features and requirements.
International
Si
Congress
DCIS 2012
960
Place
Avignon, Francia
Reviewers
Si
ISBN/ISSN
978-2-9517461-1-4
Start Date
28/11/2012
End Date
30/11/2012
From page
38
To page
43
XXVIIth Conference on Design of Circuits and Integrated Systems
Participants

Research Group, Departaments and Institutes related
  • Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
  • Departamento: Automática, Ingeniería Electrónica e Informática Industrial
  • Departamento: Ingeniería Electrónica