Observatorio de I+D+i UPM

Descripción
The integration degree achieved by nanometer technologies allows the implementation of complex applications in current FPGAs. This is the case of computations that use floating-point arithmetic, characterized by requiring large amounts of resources and long design times. One of the most used algorithms is the FFT, so an implementation of this algorithm in floating-point format is necessary to improve implemented systems and to make more powerful the new designs that will be developed in the next years. The optimization of this implementation is very useful when these devices allow the processing of long signals, at that moment floating point outperforms fixed point format. In this work three different architectures are presented and characterized in terms of resources and performance. Finally each architecture is recommended for different types of applications depending on their particular features and requirements.
Internacional	Si
Nombre congreso	DCIS 2012
Tipo de participación	960
Lugar del congreso	Avignon, Francia
Revisores	Si
ISBN o ISSN	978-2-9517461-1-4
DOI
Fecha inicio congreso	28/11/2012
Fecha fin congreso	30/11/2012
Desde la página	38
Hasta la página	43
Título de las actas	XXVIIth Conference on Design of Circuits and Integrated Systems

Esta actividad pertenece a memorias de investigación

• Autor: Javier Agustin Saenz (UPM)
• Autor: Miguel Ángel Sánchez Marcos (UPM)
• Autor: M. Luisa Lopez Vallejo (UPM)

• Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
• Departamento: Automática, Ingeniería Electrónica e Informática Industrial
• Departamento: Ingeniería Electrónica