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Abstract
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| The integration degree achieved by nanometer technologies allows the implementation of complex applications in current FPGAs. This is the case of computations that use floating-point arithmetic, characterized by requiring large amounts of resources and long design times. One of the most used algorithms is the FFT, so an implementation of this algorithm in floating-point format is necessary to improve implemented systems and to make more powerful the new designs that will be developed in the next years. The optimization of this implementation is very useful when these devices allow the processing of long signals, at that moment floating point outperforms fixed point format. In this work three different architectures are presented and characterized in terms of resources and performance. Finally each architecture is recommended for different types of applications depending on their particular features and requirements. | |
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International
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Si |
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Congress
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DCIS 2012 |
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960 |
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Place
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Avignon, Francia |
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Reviewers
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Si |
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ISBN/ISSN
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978-2-9517461-1-4 |
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Start Date
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28/11/2012 |
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End Date
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30/11/2012 |
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From page
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38 |
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To page
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43 |
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XXVIIth Conference on Design of Circuits and Integrated Systems |