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Abstract
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| This paper presents an implementation of a frequency agility algorithm for a CWFM radar, which is able to process samples in excess of 60MHz, increasing SNR in exchange of increased bandwidth or decreased distance resolution. This implementation has been realized on a Virtex5 FPGA using low cost memory chips. An experimental approach has allowed to determine the maximum sampling frequency that our implementation allows as-is, but higher speed memory chips may be used with the same HDL code, thus allowing faster sampling rates. | |
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International
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No |
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Congress
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XXVIII Simposium Nacional de la Unión Científica Internacional de Radio. 2013 |
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960 |
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Place
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Santiago de Compostela |
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Reviewers
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Si |
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ISBN/ISSN
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978-84-941537-1-6 |
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Start Date
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11/09/2013 |
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End Date
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13/09/2013 |
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From page
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95 |
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To page
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95 |
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Libro de Resúmenes y CD-ROM de Actas del Simposium |