Memorias de investigación
Communications at congresses:
Implemetación en FPGA del procesado de agilidad en frecuencia en tiempo real para un radar CWFM
Year:2013

Research Areas
  • Electronic technology and of the communications

Information
Abstract
This paper presents an implementation of a frequency agility algorithm for a CWFM radar, which is able to process samples in excess of 60MHz, increasing SNR in exchange of increased bandwidth or decreased distance resolution. This implementation has been realized on a Virtex5 FPGA using low cost memory chips. An experimental approach has allowed to determine the maximum sampling frequency that our implementation allows as-is, but higher speed memory chips may be used with the same HDL code, thus allowing faster sampling rates.
International
No
Congress
XXVIII Simposium Nacional de la Unión Científica Internacional de Radio. 2013
960
Place
Santiago de Compostela
Reviewers
Si
ISBN/ISSN
978-84-941537-1-6
Start Date
11/09/2013
End Date
13/09/2013
From page
95
To page
95
Libro de Resúmenes y CD-ROM de Actas del Simposium
Participants

Research Group, Departaments and Institutes related
  • Creador: Grupo de Investigación: Microondas y Radar
  • Departamento: Señales, Sistemas y Radiocomunicaciones