Research Publications in journals:
Using pMOS Pass-Gates to Boost SRAM Performance by Exploiting Strain Effects in Sub-20-nm FinFET Technologies
Year:2014
Research Areas
- Tools of design of integrate circuits,
- Electronic devices
Information
|
Abstract
|
|
|---|---|
| Strained fin is one of the techniques used to improve the devices as their size keeps reducing in new nanoscale nodes. In this paper, we use a predictive technology of 14 nm where pMOS mobility is significantly improved when those devices are built on top of long, uncut fins, while nMOS devices present the opposite behavior due to the combination of strains. We explore the possibility of boosting circuit performance in repetitive structures where long uncut fins can be exploited to increase fin strain impact. In particular, pMOS pass-gates are used in 6T complementary SRAM cells (CSRAM) with reinforced pull-ups. Those cells are simulated under process variability and compared to the regular SRAM. We show that when layout dependent effects are considered the CSRAM design provides 10% to 40% faster access time while keeping the same area, power, and stability than a regular 6T SRAM cell. The conclusions also apply to 8T SRAM cells. The CSRAM cell also presents increased reliability in technologies whose nMOS devices have more mismatch than pMOS transistors. | |
|
International
|
Si |
|
JCR
|
Si |
|
Title
|
Ieee Transactions on Nanotechnology |
|
ISBN
|
1536-125X |
|
Impact factor JCR
|
1,619 |
|
Impact info
|
|
|
Volume
|
|
|
|
10.1109/TNANO.2014.2354073 |
|
Journal number
|
|
|
From page
|
1226 |
|
To page
|
1233 |
|
Month
|
NOVIEMBRE |
|
Ranking
|
|
Open Access publication
Participants
- Autor: Pablo Royer Del Barrio UPM
- Autor: M. Luisa Lopez Vallejo UPM
Research Group, Departaments and Institutes related
- Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
- Departamento: Ingeniería Electrónica