Memorias de investigación
Artículos en revistas:
Using pMOS Pass-Gates to Boost SRAM Performance by Exploiting Strain Effects in Sub-20-nm FinFET Technologies
Año:2014
Áreas de investigación
  • Herramientas de diseño de circuitos integrados,
  • Dispositivos electrónicos
Datos
Descripción
Strained fin is one of the techniques used to improve the devices as their size keeps reducing in new nanoscale nodes. In this paper, we use a predictive technology of 14 nm where pMOS mobility is significantly improved when those devices are built on top of long, uncut fins, while nMOS devices present the opposite behavior due to the combination of strains. We explore the possibility of boosting circuit performance in repetitive structures where long uncut fins can be exploited to increase fin strain impact. In particular, pMOS pass-gates are used in 6T complementary SRAM cells (CSRAM) with reinforced pull-ups. Those cells are simulated under process variability and compared to the regular SRAM. We show that when layout dependent effects are considered the CSRAM design provides 10% to 40% faster access time while keeping the same area, power, and stability than a regular 6T SRAM cell. The conclusions also apply to 8T SRAM cells. The CSRAM cell also presents increased reliability in technologies whose nMOS devices have more mismatch than pMOS transistors.
Internacional
Si
JCR del ISI
Si
Título de la revista
Ieee Transactions on Nanotechnology
ISSN
1536-125X
Factor de impacto JCR
1,619
Información de impacto
Volumen
DOI
10.1109/TNANO.2014.2354073
Número de revista
Desde la página
1226
Hasta la página
1233
Mes
NOVIEMBRE
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Participantes
Grupos de investigación, Departamentos, Centros e Institutos de I+D+i relacionados
  • Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
  • Departamento: Ingeniería Electrónica