Memorias de investigación
Communications at congresses:
Execution and Verification of UML State Machines with Erlang
Year:2014

Research Areas
  • Engineering

Information
Abstract
Validation of a system design enables to discover specification errors before it is implemented (or tested), thus hopefully reducing the development cost and time. The Unified Modelling Language (UML) is becoming widely accepted for the early specification and analysis of requirements for safety-critical systems, although a better balance between UML?s undisputed flexibility, and a precise unambiguous semantics, is needed. In this paper we introduce UMerL, a tool that is capable of executing and formally verifying UML diagrams (namely, UML state machine, class and object diagrams) by means of a translation of its behavioural information into Erlang. The use of the tool is illustrated with an example in embedded software design.
International
Si
Congress
Software Engineering and Formal Methods
960
Place
Grenoble, Francia
Reviewers
Si
ISBN/ISSN
978-3-319-10431-7
Start Date
01/09/2014
End Date
05/09/2014
From page
284
To page
289
Software Engineering and Formal Methods
Participants

Research Group, Departaments and Institutes related
  • Creador: Grupo de Investigación: BABEL: Desarrollo de Software Fiable y de Alta Calidad a partir de Tecnología Declarativa
  • Departamento: Lenguajes y Sistemas Informáticos e Ingeniería de Software