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Abstract
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| When implementing digital systems on FPGAs, fixed-point arithmetic achieves improvements in area, power and operational frequency at the cost of having less accurate numerical results. To ensure the validity of the implementation, we need to verify that the numerical errors are constrained to the specified boundaries. However, modern automated analytical approaches for modelling the effects of Round-Off Noise (RON) are constrained by the type of operations they can model accurately. Control-Flow Structures (CFS) are one of the current obstacles in their applicability, as no analytical method has a direct way of dealing with them. In this paper we propose an approach based on Statistical Affine Arithmetic that is capable of modelling accurately the signal and RON in systems with CFS. Our approach adapts automatically to the structure of the design, unrolls the loops dynamically and is highly parallelizable. The experimental results show very accurate results (with variance deviations from the reference between 0.01\% and 3.37\%) in manageable times. | |
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International
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Si |
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JCR
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Si |
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Title
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Ieee Transactions on Circuits And Systems I-Regular Papers |
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ISBN
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1549-8328 |
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Impact factor JCR
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2,303 |
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Impact info
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Datos JCR del año 2013 |
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Volume
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Journal number
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From page
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- |
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To page
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- |
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Month
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SIN MES |
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