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Descripción
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| When implementing digital systems on FPGAs, fixed-point arithmetic achieves improvements in area, power and operational frequency at the cost of having inaccurate numerical results. To ensure that these errors will not render the circuit useless, we need to verify that the numerical errors are constrained to the specified boundaries. However, as the number of operations in the targeted designs increases, the automated analytical approaches for modelling the effects of round-off noise become more complex. Thus, most modern evaluation tools lack the ability to scale properly, incurring in either inaccurate characterizations or impractically long execution times. In this paper we propose a technique based on Statistical Affine Arithmetic that can scale to larger designs without impacting the accuracy of the results while achieving low execution times. Our approach adapts automatically to the structure of the design and is highly parallelizable. The experimental results show negligible impact on the accuracy of the results with execution time improvements of 40% and higher with respect to previous techniques. | |
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Internacional
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No |
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JCR del ISI
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No |
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Título de la revista
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Ieee Transactions on Circuits And Systems. II, Express Briefs |
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ISSN
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1549-7747 |
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