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Descripción
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| In the recent developments in the field of III-V on Si dual-junction solar cells, low attention has been paid to optimizing the device configuration to maximize its photovoltaic performance. The few practical implementations reported heretofore have been based on III-V solar cell processing techniques. Although the fabrication of conventional Si structures is a well-known technology, certain steps have been found to be incompatible with III-V semiconductors, primarily due to their high thermal load. Accordingly, in this work we discuss the applicability of different alternatives for the Si rear-surface passivation (Al-BSF, PERC- and HIT-like schemes) in III-V/Si dual-junction solar cell structures. Using numerical simulations, a comparison of the Si bottom cell performance in a GaAsP/Si dual-junction solar cell structure is presented for the mentioned alternatives. | |
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Internacional
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Si |
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Nombre congreso
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42nd IEEE Photovoltaic Specialist Conference, |
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Tipo de participación
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960 |
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Lugar del congreso
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New Orleans; EEUU |
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Revisores
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Si |
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ISBN o ISSN
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978-1-4799-7944-8 |
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DOI
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10.1109/pvsc.2015.7356235 |
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Fecha inicio congreso
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14/06/2015 |
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Fecha fin congreso
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19/06/2015 |
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Desde la página
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1 |
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Hasta la página
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4 |
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Título de las actas
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Proc. PVSC 2015 |