Observatorio de I+D+i UPM

Memorias de investigación
Otras publicaciones:
ANN IP core
Áreas de investigación
  • Diseño de circuitos integrados digitales
This IP core is a configurable feedforward Artificial Neural Network (ANN). ANNs are Artificial Intelligence (AI) algorithms biologically inspired on the brain. An ANN can be trained to learn a specific task. Typical tasks are pattern recognition and classification, but not exclusively. ANN is based on a simple model of a neuron. Neuron?s models are grouped by layers are connected in a network. This IP performs full feedforward connections between consecutive layers. All neurons? outputs of a layer become the inputs for the next layer. This ANN architecture is also known as Multi-Layer Perceptron (MLP) when is trained with a supervised learning algorithm. Different kinds of activation functions can be added easily coding them in the provided VHDL template. This IP core is provided in two parts: kernel plus wrapper. The kernel is the optimized ANN with basic logic interfaces. The kernel should be instantiated inside a wrapper to connect it with the user?s system buses. Currently, an example wrapper is provided for instantiate it on Xilinx Vivado, which uses AXI4 interfaces for AMBA buses. Developers hope to add more wrappers in the future with the help of the OpenCores community.
Tipo de publicación
Hardware IP core libre
Esta actividad pertenece a memorias de investigación
  • Autor: David Aledo Ortega (UPM)
  • Autor: Felix Antonio Moreno Gonzalez (UPM)
Grupos de investigación, Departamentos, Centros e Institutos de I+D+i relacionados
  • Creador: Grupo de Investigación: Electrónica Industrial
  • Centro o Instituto I+D+i: Centro de Electrónica Industrial. CEI
  • Departamento: Automática, Ingeniería Eléctrica y Electrónica e Informática Industrial
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Cofinanciación del MINECO en el marco del Programa INNCIDE 2011 (OTR-2011-0236)
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