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Descripción
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| Design and development of hard Real-Time (RT) embedded systems present several crucial requirements regarding criti- cality and timeliness of these systems. Formal methods have been presented as a promising alternative to deal with the design issues of these applications. However, these formal method do not scale well in complex systems. Modeling and Simulation (M&S) provides cost-effective approaches to verify and validate the design and implementation details of complex RT applications. Nevertheless, M&S approaches and artifacts are usually discarded in the later phases of the development. Discrete Event Systems Specification (DEVS) provides an appropriate M&S framework to provide formal specifications to the actual RT system, incrementally moving from software specifications to a full hardware embedded sys- tem. In this work, we propose a hardware-in-the-loop model- driven method, based on DEVS for RT/embedded applica- tion/systems engineering. Our approach is based on an in- cremental substitution of DEVS virtual software models with Unix-compliant device files through a formally defined pro- cess in the modeling phase. Consequently, any DEVS simu- lation engine can be used. This paper advances the state-of- the-art in hardware-software co-design methodologies. | |
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Internacional
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Si |
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Nombre congreso
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Summer Computer Simulation Conference (SummerSim-SCSC 2016) |
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Tipo de participación
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960 |
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Lugar del congreso
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Montreal, QC, Canada |
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Revisores
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Si |
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ISBN o ISSN
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978-1-5108-2424-9 |
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DOI
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Fecha inicio congreso
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24/07/2016 |
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Fecha fin congreso
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27/07/2016 |
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Desde la página
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1 |
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Hasta la página
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8 |
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Título de las actas
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Proceedings of the Summer Computer Simulation Conference, SummerSim 2016 |