Observatorio de I+D+i UPM

Descripción
This brief presents a novel 4096-point radix-4 memory-based fast Fourier transform (FFT). The proposed architecture follows a conflict-free strategy that only requires a total memory of size N and a few additional multiplexers. The control is also simple, as it is generated directly from the bits of a counter. Apart from the low complexity, the FFT has been implemented on a Virtex-5 field programmable gate array (FPGA) using DSP slices. The goal has been to reduce the use of distributed logic, which is scarce in the target FPGA. With this purpose, most of the hardware has been implemented in DSP48E. As a result, the proposed FPGA is efficient in terms of hardware resources, as is shown by the experimental results.
Internacional	Si
JCR del ISI	Si
Título de la revista	Ieee Transactions on Very Large Scale Integration (Vlsi) Systems
ISSN	1063-8210
Factor de impacto JCR	1,698
Información de impacto
Volumen
DOI	10.1109/TVLSI.2016.2567784
Número de revista
Desde la página	375
Hasta la página	379
Mes	ENERO
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Esta actividad pertenece a memorias de investigación

• Autor: Mario Garrido (Lund University)
• Autor: Miguel Angel Sanchez
• Autor: M. Luisa Lopez Vallejo (UPM)
• Autor: Jesus Grajal De la Fuente (UPM)

• Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
• Centro o Instituto I+D+i: Centro de I+d+i en Procesado de la Información y Telecomunicaciones
• Departamento: Ingeniería Electrónica
• Departamento: Señales, Sistemas y Radiocomunicaciones