Descripción
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Execution times of FPGA streaming architectures that implement large DFGs and process large datasets, as in CFD simulations that compute meshes iteratively, are mostly determined by the long data transfers between external memory and FPGA. Whenever the datasets consist of variable-length data packets (i.e. when processing unstructured meshes), the common approach that forces all packets to have the longest length in order to facilitate stream decoding decreases overall performance due to the increased size of the data stream. In this paper, the design of a high performance decoder of variable-length data packets is presented. It is based on a general data frame structure and it enhances performance through optimized pipelining and distributed flow control. Results on a Stratix 10 device show working frequencies above 400 MHz with estimated speedups between 2.4 and 3.8 over an equivalent fixed-length decoder. | |
Internacional
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Si |
Nombre congreso
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29th International Conference on Field-Programmable Logic and Applications, FPL?19 |
Tipo de participación
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OTHERS |
Lugar del congreso
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Barcelona |
Revisores
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Si |
ISBN o ISSN
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978-1-5386-8517-4 |
DOI
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Fecha inicio congreso
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09/09/2019 |
Fecha fin congreso
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11/09/2019 |
Desde la página
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1 |
Hasta la página
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6 |
Título de las actas
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Proceedings of the 29th International Conference on Field-Programmable Logic and Application |