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Memorias de investigación
Artículos en revistas:
On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming
Año:2018
Áreas de investigación
  • Ingeniería eléctrica, electrónica y automática
Datos
Descripción
Evolvable hardware allows the generation of circuits that are adapted to specific problems by using an evolutionary algorithm (EA). Dynamic partial reconfiguration of FPGA LUTs allows making the processing elements (PEs) of these circuits small and compact, thus allowing large scale circuits to be implemented in a small FPGA area. This facilitates the use of these techniques in embedded systems with limited resources. The improvement on resource-efficient implementation techniques has allowed increasing the size of processing architectures from a few PEs to several hundreds. However, these large sizes pose new challenges for the EA and the architecture, which may not be able to take full advantage of the computing capabilities of its PEs. In this article, two different topologies?systolic array (SA) and Cartesian genetic programming (CGP)?are scaled from small to large sizes and analyzed, comparing their behavior and efficiency at different sizes. Additionally, improvements on SA connectivity are studied. Experimental results show that, in general, SA is considerably more resource-efficient than CGP, needing up to 60% fewer FPGA resources (LUTs) for a solution with similar performance, since the LUT usage per PE is 5 times smaller. Specifically, 10 × 10 SA has better performance than 5 × 10 CGP, but uses 50% fewer resources.
Internacional
Si
JCR del ISI
Si
Título de la revista
Genetic Programming And Evolvable Machines
ISSN
1389-2576
Factor de impacto JCR
1,514
Información de impacto
Datos JCR del año 2016
Volumen
DOI
10.1007/s10710-018-9340-5
Número de revista
Desde la página
1
Hasta la página
32
Mes
OCTUBRE
Ranking
Esta actividad pertenece a memorias de investigación
Participantes
  • Autor: Javier Mora De Sambricio (UPM)
  • Autor: Ruben Salvador Perea (UPM)
  • Autor: Eduardo de la Torre Arnanz (UPM)
Grupos de investigación, Departamentos, Centros e Institutos de I+D+i relacionados
  • Creador: Centro o Instituto I+D+i: Centro de Investigación en Tecnologías del Software y Sistemas Multimedia para la Sostenibilidad (CITSEM)
  • Centro o Instituto I+D+i: Centro de Electrónica Industrial. CEI
  • Departamento: Automática, Ingeniería Eléctrica y Electrónica e Informática Industrial
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