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Descripción
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| In the era of Cyber Physical Systems, designers need to offer support for run-time adaptivity considering different constraints, including the internal status of the system. This work presents a run-time monitoring approach, based on the Performance Application Programming Interface, that offers a unified interface to transparently access both the standard Performance Monitoring Counters (PMCs) in the CPUs and the custom ones integrated into hardware accelerators. Automatic tools offer to Sw programmers the support to design and implement Coarse-Grain Virtual Reconfigurable Circuits, instrumented with custom PMCs. This approach has been validated on a heterogeneous application for image/video processing with an overhead of 6% of the execution time. | |
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Internacional
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Si |
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Nombre congreso
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FSP Workshop 2019; Sixth International Workshop on FPGAs for Software Programmers |
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Tipo de participación
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960 |
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Lugar del congreso
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Barcelona, España |
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Revisores
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Si |
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ISBN o ISSN
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978-3-8007-5045-0 |
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DOI
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Fecha inicio congreso
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12/09/2019 |
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Fecha fin congreso
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12/09/2019 |
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Desde la página
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1 |
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Hasta la página
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10 |
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Título de las actas
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FSP Workshop 2019; Sixth International Workshop on FPGAs for Software Programmers |