Memorias de investigación
Communications at congresses:
Variance reduction techniques for Monte Carlo simulations. A parameterizable FPGA approach
Year:2008

Research Areas
  • Electronics engineering

Information
Abstract
In this work we present how variance reduction techniques can be applied to Monte Carlo simulations on an FPGA platform. Variance reduction techniques improve the accuracy of Monte Carlo simulations without increasing the number of individual simulations required, and consequently, the time and resources needed. Two techniques, Stratified Sampling and Latin Hypercube, have been implemented with a parameterizable architecture that additionally allows different configurations. To verify the proposed approach we have integrated these techniques on an FPGA Gaussian Random Number Generator, obtaining a complete a hardware accelerator for Monte Carlo simulations.
International
Si
Congress
Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on
960
Place
Reviewers
No
ISBN/ISSN
978-1-4244-2181-7
Start Date
31/08/2008
End Date
03/09/2008
From page
1296
To page
1299
Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on
Participants

Research Group, Departaments and Institutes related
  • Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
  • Departamento: Ingeniería Electrónica