Observatorio de I+D+i UPM

Descripción
In this work we present how variance reduction techniques can be applied to Monte Carlo simulations on an FPGA platform. Variance reduction techniques improve the accuracy of Monte Carlo simulations without increasing the number of individual simulations required, and consequently, the time and resources needed. Two techniques, Stratified Sampling and Latin Hypercube, have been implemented with a parameterizable architecture that additionally allows different configurations. To verify the proposed approach we have integrated these techniques on an FPGA Gaussian Random Number Generator, obtaining a complete a hardware accelerator for Monte Carlo simulations.
Internacional	Si
Nombre congreso	Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on
Tipo de participación	960
Lugar del congreso
Revisores	No
ISBN o ISSN	978-1-4244-2181-7
DOI
Fecha inicio congreso	31/08/2008
Fecha fin congreso	03/09/2008
Desde la página	1296
Hasta la página	1299
Título de las actas	Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on

Esta actividad pertenece a memorias de investigación

• Autor: José María Pesquero (BBVA)
• Autor: M. Luisa Lopez Vallejo (UPM)
• Autor: Pedro Echevarria Aramendi (UPM)

• Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
• Departamento: Ingeniería Electrónica