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Descripción
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| Monte Carlo financial simulation relies on the generation of random variables with different probability distribution functions. These simulations, particularly the random number generator (RNG) cores, are computationally intensive and are ideal candidates for hardware acceleration. In this work we present an FPGA based Log-normal RNG ideally suited for financial Monte Carlo simulations, as it is run-time parameterisable and compatible with variance reduction techniques. Our architecture achieves a throughput of one sample per cycle with a 227.6 MHz clock on a Xilinx Virtex-4 FPGA. | |
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Internacional
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Si |
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Nombre congreso
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4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications |
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Tipo de participación
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960 |
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Lugar del congreso
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Revisores
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Si |
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ISBN o ISSN
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978-3-540-78609-2 |
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DOI
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Fecha inicio congreso
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05/03/2009 |
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Fecha fin congreso
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08/03/2008 |
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Desde la página
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221 |
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Hasta la página
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232 |
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Título de las actas
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Lecture Notes In Computer Science; Vol. 4943 |