Observatorio de I+D+i UPM

Descripción
Monte Carlo financial simulation relies on the generation of random variables with different probability distribution functions. These simulations, particularly the random number generator (RNG) cores, are computationally intensive and are ideal candidates for hardware acceleration. In this work we present an FPGA based Log-normal RNG ideally suited for financial Monte Carlo simulations, as it is run-time parameterisable and compatible with variance reduction techniques. Our architecture achieves a throughput of one sample per cycle with a 227.6 MHz clock on a Xilinx Virtex-4 FPGA.
Internacional	Si
Nombre congreso	4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Tipo de participación	960
Lugar del congreso
Revisores	Si
ISBN o ISSN	978-3-540-78609-2
DOI
Fecha inicio congreso	05/03/2009
Fecha fin congreso	08/03/2008
Desde la página	221
Hasta la página	232
Título de las actas	Lecture Notes In Computer Science; Vol. 4943

Esta actividad pertenece a memorias de investigación

• Participante: Wayne Luk ( Dept. of Computing, Imperial College London, (United Kingdom))
• Autor: M. Luisa Lopez Vallejo (UPM)
• Autor: David B. Thomas ( Dept. of Computing, Imperial College London, (United Kingdom))
• Autor: Pedro Echevarria Aramendi (UPM)

• Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
• Departamento: Ingeniería Electrónica