Memorias de investigación
Communications at congresses:
An FPGA Run-Time Parameterisable Log-Normal Random Number Generator
Year:2008

Research Areas
  • Electronics engineering

Information
Abstract
Monte Carlo financial simulation relies on the generation of random variables with different probability distribution functions. These simulations, particularly the random number generator (RNG) cores, are computationally intensive and are ideal candidates for hardware acceleration. In this work we present an FPGA based Log-normal RNG ideally suited for financial Monte Carlo simulations, as it is run-time parameterisable and compatible with variance reduction techniques. Our architecture achieves a throughput of one sample per cycle with a 227.6 MHz clock on a Xilinx Virtex-4 FPGA.
International
Si
Congress
4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
960
Place
Reviewers
Si
ISBN/ISSN
978-3-540-78609-2
Start Date
05/03/2009
End Date
08/03/2008
From page
221
To page
232
Lecture Notes In Computer Science; Vol. 4943
Participants
  • Participante: Wayne Luk Dept. of Computing, Imperial College London, (United Kingdom)
  • Autor: M. Luisa Lopez Vallejo UPM
  • Autor: David B. Thomas Dept. of Computing, Imperial College London, (United Kingdom)
  • Autor: Pedro Echevarria Aramendi UPM

Research Group, Departaments and Institutes related
  • Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
  • Departamento: Ingeniería Electrónica