Observatorio de I+D+i UPM

Descripción
In this paper we address the time-constrained architectural synthesis of fixed-point DSP algorithms using FPGA devices. Optimized fixed-point implementations are obtained by means of considering: (i) a multiple wordlength approach; (ii) a complete datapath formed of wordlength-wise resources (i.e. functional units, multiplexers and registers); and, (iii) a novel resource usage metric that enables the wise distribution of logic fabric and embedded DSP resources. The paper shows: (i) the benefits of applying a multiple wordlength approach to the implementation of fixedpoint datapaths; and (ii) the benefits of a wise use of embedded FPGA resources. The proposed metric enables area improvements up to 54% and the use of a complete fixed-point datapath leads to improvements up to 35%.
Internacional	Si
Nombre congreso	International Conference on Reconfigurable Computing and FPGAs, RECONFIG'08
Tipo de participación	960
Lugar del congreso	Cancún (México)
Revisores	Si
ISBN o ISSN
DOI
Fecha inicio congreso	03/12/2008
Fecha fin congreso	05/12/2008
Desde la página	0
Hasta la página	0
Título de las actas	Proceedings of the International Conference on Reconfigurable Computing and FPGAs, RECONFIG'08

Esta actividad pertenece a memorias de investigación

• Participante: Gerardo Leyva (Universidad Aut?onoma de Aguascalientes, Mexico)
• Autor: Juan Antonio Lopez Martin (UPM)
• Autor: Octavio Nieto-Taladriz Garcia (UPM)
• Autor: Gabriel Caffarena Fernandez (UPM)
• Autor: Carlos Carreras Vaquer (UPM)

• Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
• Departamento: Ingeniería Electrónica