Observatorio de I+D+i UPM

Descripción
In this paper we address the automatic synthesis of DSP algorithms using FPGAs. Optimized fixed-point implementations are obtained by means of considering: (i) a multiple wordlength approach; (ii) a complete datapath formed of wordlength-wise resources (i.e. functional units, multiplexers and registers); and, (ii) an FPGA-wise resource usage metric that enables an efficient distribution of logic fabric and embedded DSP resources. The paper shows: (i) the benefits of applying a multiple wordlength approach to the implementation of fixed-point datapath; and (ii) the benefits of a wise use of embedded FPGA resources. The use of a complete fixed-point datapath leads to improvements up to 35%. And, the wise mapping of opertaions to FPGA resources (logic fabric and embedded blocks), thanks to the proposed resource usage metric, leads to improvements up to 54%.
Internacional	Si
JCR del ISI	No
Título de la revista	International Journal of Reconfigurable Computing
ISSN	1687-7195
Factor de impacto JCR	0
Información de impacto
Volumen	2009
DOI	10.1155/2009/703267
Número de revista	0
Desde la página	1
Hasta la página	14
Mes	AGOSTO
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• Autor: Gabriel Caffarena Fernandez (UPM)
• Autor: Juan Antonio Lopez Martin (UPM)
• Autor: Carlos Carreras Vaquer (UPM)
• Autor: Octavio Nieto-Taladriz Garcia (UPM)

• Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
• Departamento: Ingeniería Electrónica