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Descripción
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| Studying fundamental Computer Architecture and Organization topics requires a significant amount of practical work if students are to acquire a good grasp of the theoretical concepts presented in classroom lectures or textbooks. The use of simulators is commonly adopted in order to reach this objective. However, as most of the available educational simulators focus on specific topics, different laboratory assignments usually require the use of different simulators. This paper presents a graphical and interactive reduced instruction set computer (RISC) processor and memory simulator that allows active learning of some theoretical concepts covered in Computer Architecture and Organization courses. The simulator can be configured to present different processor views, from a simple serial one, without caches or pipelines, to a more realistic one with caches and superscalar execution. This approach allows a set of increasingly complex code-based laboratory assignments to be developed using a single simulator, covering topics ranging from assembly language programming to the analysis of the different kind of cache misses, pipeline hazards or branch prediction hits and misses produced during a program execution. The simulator has been included in a an automatic assessment system that helps the students to complete the assignments and helps teachers to evaluate the correctness of the students¿ solutions in different environments, such as high-enrollment courses or distance education. Since 1996, both the simulator and the automatic assessment system have been successfully used by more than 5000 students in Computer Architecture and Organization courses at the Technical University of Madrid (UPM), Spain. | |
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Internacional
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Si |
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JCR del ISI
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Si |
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Título de la revista
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IEEE TRANSACTIONS ON EDUCATION |
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ISSN
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0018-9359 |
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Factor de impacto JCR
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1,4 |
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Información de impacto
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Volumen
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52 |
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DOI
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10.1109/TE.2008.927690 |
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Número de revista
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2 |
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Desde la página
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248 |
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Hasta la página
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256 |
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Mes
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MAYO |
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Ranking
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