Observatorio de I+D+i UPM

Memorias de investigación
Ponencias en congresos:
Precision-Wise Architectural Synthesis of DSP Circuits
Año:2010
Áreas de investigación
  • Microelectrónica
Datos
Descripción
This paper addresses the combination of wordlength optimization and architectural synthesis as a single design task, aiming at reducing the area of FPGA implementations. These two well-known design tasks are commonly applied sequentially. On one hand, wordlength optimization¿s goal is to find the fixed-point format of signals that minimizes cost. On the other hand, architectural synthesis optimizes the architecture of the implementation of an algorithm. These two tasks are highly interdependent, since the wordlength minimization depends on the architecture and the architectural synthesis final output depends on the initial signal wordlengths. By combining them, a wider exploration of the design space can be performed. A fine-grain combined wordlength optimization and architectural synthesis based on the use of simulated annealing is presented. The optimizer is tuned for DSP algorithms and is able to simultaneously optimize in terms of implementation area and output noise, thus leading to significant improvements. A complete comparison between the traditional sequential approach and the proposed combined approach is provided. Area improvements of up to 21% are reported.
Internacional
Si
Nombre congreso
European Signal Processing Conference
Tipo de participación
960
Lugar del congreso
Aalborg (Dinamarca)
Revisores
Si
ISBN o ISSN
2076-1465
DOI
Fecha inicio congreso
23/08/2010
Fecha fin congreso
27/08/2010
Desde la página
1
Hasta la página
5
Título de las actas
Proceedings of the European Signal Processing Conference, EUSIPCO'10
Esta actividad pertenece a memorias de investigación
Participantes
  • Autor: Gabriel Caffarena Fernandez (UPM)
  • Autor: Carlos Carreras Vaquer (UPM)
Grupos de investigación, Departamentos, Centros e Institutos de I+D+i relacionados
  • Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
  • Departamento: Ingeniería Electrónica
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