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Descripción
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| This paper presents a novel high-level analytical approach to estimate logic power consumption of multipliers implemented in FPGAs in the presence of glitching and correlation. The proposed methodology is based on: 1) an analytical model for the switching activity of the component, and 2) a structural analysis of the FPGA implementation of the component. The complete model is parameterized in terms of complexity factors such as word-lengths and signal statistics of the operands. It also accounts for the glitching introduced by the component parts that exhibit the highest switching activity. Compared to the other power estimation methods, the number of circuit simulations needed for characterizing the power model of the component is highly reduced. The results show that the accuracy of the model is within 10% of low-level power estimates given by the tool XPower and that it achieves better performance than other proposed high-level approaches. | |
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Internacional
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Si |
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Nombre congreso
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15th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA'07 |
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Tipo de participación
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960 |
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Lugar del congreso
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Monterey (California) USA |
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Revisores
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Si |
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ISBN o ISSN
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978-1-59593-600-4 |
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DOI
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Fecha inicio congreso
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18/02/2007 |
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Fecha fin congreso
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20/02/2007 |
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