Communications at congresses:
Area-Efficient Linear Regression Architecture for Real-Time Signal Processing on FPGAs
Year:2011
Research Areas
- Electronics engineering
Information
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Abstract
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| Linear regression is a technique widely used in digital signal processing. It consists on finding the linear function that better fits a given set of samples. This paper proposes different hardware architectures for the implementation of the linear regression method on FPGAs, specially targeting area restrictive systems. It saves area at the cost of constraining the lengths of the input signal to some fixed values. We have implemented the proposed scheme in an Automatic Modulation Classifier, meeting the hard real-time constraints this kind of systems have. | |
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International
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Si |
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Congress
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Design of Circuits and Integrated Systems |
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960 |
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Place
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Albufeira, Portugal |
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Reviewers
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Si |
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ISBN/ISSN
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978-972-99181-3-1 |
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Start Date
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16/11/2011 |
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End Date
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18/11/2011 |
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From page
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333 |
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To page
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338 |
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Design of Circuits and Integrated Systems |
Open Access publication
Participants
- Autor: Pablo Royer Del Barrio UPM
- Autor: Miguel Ángel Sánchez Marcos UPM
- Autor: M. Luisa Lopez Vallejo UPM
- Autor: Carlos Alberto Lopez Barrio UPM
Research Group, Departaments and Institutes related
- Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)
- Departamento: Ingeniería Electrónica