Observatorio de I+D+i UPM
• ESPAÑOL
• ENGLISH
INVESTIGADORES
ESTRUCTURAS DE I+D+I
ACTIVIDAD INVESTIGADORA
INNOVACIÓN
Investigador
M. Luisa Lopez Vallejo
Categoría Investigador
CATEDRATICO UNIVERSIDAD
Escuela UPM
E.T.S. DE INGENIEROS DE TELECOMUNICACION
Departamento:
INGENIERÍA ELECTRÓNICA (N)
Centros/Institutos I+D+i
CENTRO I+D+I PROC. INFORMACIÓN Y TELECOM
Area Conocimiento
TECNOLOGIA ELECTRONICA
Grupo de Investigación:
Laboratorio de Sistemas Integrados (LSI)
Email (Directorio UPM)
m.lopez.vallejo
upm.es
Teléfono (Directorio UPM)
910672237
Datos de Memorias relacionados
Proyectos de I+D+i y generación de recursos
42 Proyectos de I+D+i
1: (2007)
ANÁLISIS E INVESTIGACIÓN DE ACELERACIÓN DE VALORACIÓN FINANCIERA MEDIANTE PLATAFORMAS RECONFIGURABLES
2: (2007)
OPTIMA: Optimización de Consumo y Temperatura en Arquitecturas Complejas (TEC2006-00739)
3: (2007)
Sistemas Integrados para Entornos Inteligentes (SINTEI-2)
4: (2008)
Arquitecturas Digitales de Altas Prestaciones
5: (2008)
Estudio y Desarrollo de Sistemas de Guerra Electrónica
6: (2008)
OPTIMA: Optimización de Consumo y Temperatura en Arquitecturas Complejas
7: (2009)
ANÁLISIS E INVESTIGACIÓN DE ACELERACIÓN DE VALORACIÓN FINANCIERA MEDIANTE PLATAFORMAS RECONFIGURABLES.
8: (2009)
ARQUITECTURA DIGITALES DE ALTAS PRESTACIONES
9: (2009)
ESTUDIO Y DESARROLLO DE SISTEMAS DE GUERRA ELECTRONICA
10: (2009)
ESTUDIO Y DESARROLLO DE SISTEMAS DE GUERRA ELECTRÓNICA.
11: (2009)
Optimización de consumo y temperatura en arquitecturas complejas
12: (2010)
ANÁLISIS E INVESTIGACIÓN DE ACELERACIÓN DE VALORACIÓN FINANCIERA MEDIANTE PLATAFORMAS RECONFIGURABLES.
13: (2010)
DISEÑO ELECTRONICO AVANZADO: CONSULO, TEMPERATURA Y ALTAS PRESTACIONES
14: (2010)
ESTUDIO Y DESARROLLO DE SISTEMAS DE GUERRA ELECTRONICA
15: (2010)
OPTIMIZACION DE CONSUMO Y TEMPERATURA EN ARQUITECTURAS COMPLEJAS
16: (2011)
BASYLIS: moBile, Autonomous and affordable SYstem to increase safety in Large unpredIctable environmentS
17: (2011)
DISEÑO ELECTRONICO AVANZADO: CONSULO, TEMPERATURA Y ALTAS PRESTACIONES
18: (2011)
ESTUDIO Y DESARROLLO DE SISTEMAS DE GUERRA ELECTRONICA
19: (2013)
BASYLIS
20: (2013)
RADHARQ: DESARROLLO DE TECNOLOGÍA RESISTENTE A LA RADIACIÓN PARA MICROELECTRONICA ESPACIAL
21: (2013)
RED ESPAÑOLA DE VARIABILIDAD EN TECNOLOGIAS, CIRCUITOS Y SISTEMAS MICRO/NANOELECTRONICOS
22: (2013)
TOLERANCIA A VARIACIONES PVT Y RADIACIÓN EN TECNOLOGÍAS NANOMETRICAS
23: (2014)
BASYLIS
24: (2014)
BASYLIS
25: (2014)
RADHARQ: DESARROLLO DE TECNOLOGÍA RESISTENTE A LA RADIACIÓN PARA MICROELECTRONICA ESPACIAL
26: (2014)
TOLERANCIA A VARIACIONES PVT Y RADIACIÓN EN TECNOLOGÍAS NANOMETRICAS
27: (2015)
RADHARQ: DESARROLLO DE TECNOLOGÍA RESISTENTE A LA RADIACIÓN PARA MICROELECTRONICA ESPACIAL
28: (2015)
TOLERA: Tolerancia a variaciones PVT y radiación en tecnologías nanométricas
29: (2016)
SOPORTE A LA DEFINICIÓN, DISEÑO, DESARROLLO Y VALIDACIÓN DE UNA BIBLIOTECA MICROELECTRÓNICA DE CÉLULAS ESTÁNDAR ENDURECIDA FRENTE A RADIACIÓN, COMPATIVLE CON LA TECNOLOGÍA IHP SGB25RH
30: (2016)
TOLERANCIA A VARIACIONES PVT Y RADIACIÓN EN TECNOLOGÍAS NANOMETRICAS
31: (2016)
TOLERA-2: Variabilidad en tecnologías nanométricas: tolerancia, fiabilidad y aprovechamiento
32: (2016)
VARIABILIDAD EN TECNOLOGIAS NANOMETRICAS: TOLERANCIA, FIABILIDAD Y APROVECHAMIENTO (TOLERA-2)
33: (2017)
SOPORTE A LA DEFINICIÓN, DISEÑO, DESARROLLO Y VALIDACIÓN DE UNA BIBLIOTECA MICROELECTRÓNICA DE CÉLULAS ESTÁNDAR ENDURECIDA FRENTE A RADIACIÓN, COMPATIVLE CON LA TECNOLOGÍA IHP SGB25RH
34: (2017)
TOLERANCIA A VARIACIONES PVT Y RADIACIÓN EN TECNOLOGÍAS NANOMETRICAS
35: (2017)
VARIABILIDAD EN TECNOLOGIAS NANOMETRICAS: TOLERANCIA, FIABILIDAD Y APROVECHAMIENTO (TOLERA-2)
36: (2018)
Desarrollo Algoritmo Mod Intrapulso
37: (2018)
SOPORTE A LA DEFINICIÓN, DISEÑO, DESARROLLO Y VALIDACIÓN DE UNA BIBLIOTECA MICROELECTRÓNICA DE CÉLULAS ESTÁNDAR ENDURECIDA FRENTE A RADIACIÓN, COMPATIVLE CON LA TECNOLOGÍA IHP SGB25RH
38: (2018)
VARIABILIDAD EN TECNOLOGIAS NANOMETRICAS: TOLERANCIA, FIABILIDAD Y APROVECHAMIENTO (TOLERA-2)
39: (2019)
Desarrollo Algoritmo Mod Intrapulso
40: (2019)
NEUROWARE: Efficient and Robust Hardware for Brain-Inspired Computin
41: (2019)
VARIABILIDAD EN TECNOLOGIAS NANOMETRICAS: TOLERANCIA, FIABILIDAD Y APROVECHAMIENTO (TOLERA-2)
42: (2019)
Variability in Nanometric technologies: Tolerance, Reliability and Benefits
Formación de Investigadores y Movilidad
5 Estancias y sabáticos recogidos en programas oficiales
1: (2015)
Sabático en el MTL (MIT) 2015-2016
2: (2016)
Sabático en MIT (EEUU), grupo del Prof. A. Chandrakasan
3: (2017)
Estancia en el MIT (EEUU)
4: (2018)
Design of advanced digital circuits with GaN technology
5: (2019)
Estancia de investigación en MIT
8 Tesis Doctorales
1: (2011)
HARDWARE ACCELERATION OF MONTE CARLO-BASED SIMULATIONS
2: (2012)
Implementación de algoritmos de procesado de señal sobre FPGA: Especificación, Reutilización y Exploración del espacio de diseño
3: (2012)
On-Chip Thermal Monitoring: Design, Placement and Interconnection of Temperature Sensors
4: (2015)
Design and Simulation of Deep Nanometer SRAM Cells under Energy, Mismatch, and Radiation Constraints
5: (2015)
Fault management techniques for systems with SRAM-based FPGAs.
6: (2017)
Modeling and design of ring oscillators and their application in radiation environments.
7: (2017)
Resistive RAM: simulation and modeling for reliable design
8: (2017)
Study, design and validation of a framework model for smoke and particle-filled atmospheres
Difusión de Resultados de Investigación
70 Artículos en revistas
1: (2007)
Energy-Aware Compilation and Hardware Design for VLIW Embedded Systems
2: (2008)
A hardware mechanism to reduce the energy consumption of the register file of in-order architectures
3: (2008)
A Nanowatt Smart Thermal Sensor for Dynamic Temperature Management
4: (2008)
Further Specialization of Clustered VLIW Processors: A MAP Decoder for Software Defined Radio
5: (2008)
Implementing FFT-Based Digital Channelized Receivers on FPGA Platforms
6: (2008)
Implementing FFT-based digital channelized receivers on FPGA platforms
7: (2008)
Joint hardware¿software leakage minimization approach for the register file of VLIW embedded architectures
8: (2008)
Power Considerations in Banked CAMs: A leakage Reduction Approach
9: (2010)
Thermal analysis and modeling of embedded processors
10: (2010)
Thermal analysis and modeling of embedded processors
11: (2011)
A Light-Weight On-Chip Monitoring Network for Dynamic Adaptation and Calibration
12: (2011)
Customizing floating-point units for FPGAs: Area-performance-standard trade-offs
13: (2011)
Customizing floating-point units for FPGAs: Area-performance-standard trade-offs
14: (2011)
Customizing floating-point units for FPGAs: Area-performance-standard trade-offs
15: (2011)
Customizing floating-point units for fpgas: Area-performance-standard trade-offs
16: (2012)
A Light-Weight On-Chip Monitoring Network for Dynamic Adaptation and Calibration
17: (2012)
High Performance FPGA-oriented Mersenne Twister Uniform Random Number Generator
18: (2012)
Improving Hardware Reuse through XML-based Interface Encapsulation
19: (2012)
Light-Weight On-Chip Monitoring Network for Dynamic Adaptation and Calibration
20: (2013)
A Low-Area Reference-Free Power Supply Sensor
21: (2013)
A 0.0016 mm(2) 0.64 nJ Leakage-Based CMOS Temperature Sensor
22: (2013)
A 0.0016 mm(2) 0.64 nJ Leakage-Based CMOS Temperature Sensor
23: (2013)
Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers
24: (2013)
Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers
25: (2013)
Floating-Point Exponentiation Units for Reconfigurable Computing
26: (2013)
High Performance FPGA-oriented Mersenne Twister Uniform Random Number Generator
27: (2013)
Ratio-Based Temperature-Sensing Technique Hardened Against Nanometer Process Variations
28: (2014)
A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs)
29: (2014)
A Tool for the Automatic Analysis of Single Events Effects on Electronic Circuits
30: (2014)
Building Memristor Applications: From Device Model to Circuit Design
31: (2014)
Four-Injector Variability Modeling of FinFET Predictive Technology Models
32: (2014)
Real-time radar pulse parameter extractor
33: (2014)
System Design Framework and Methodology for Xilinx Virtex FPGA Configuration Scrubbers
34: (2014)
Using pMOS Pass-Gates to Boost SRAM Performance by Exploiting Strain Effects in Sub-20-nm FinFET Technologies
35: (2015)
A Dual-Layer Fault Manager for Systems based on Xilinx Virtex FPGAs
36: (2015)
A Survey on Theoretical and Practical Aspects of Imaging Aids for Artificial Vision in Professional Environments
37: (2015)
A Thermal Adaptive Scheme for Reliable Write Operation on RRAM Based Architectures
38: (2015)
A time-resolved Monte Carlo smoke model for use at optical and infrared frequencies
39: (2015)
An In-Depth Analysis of Ring Oscillators: Exploiting Their Configurable Duty-Cycle
40: (2015)
Design and Characterization of a Built-In CMOS TID Smart Sensor
41: (2015)
Evolution of Radiation-Induced Soft Errors in FinFET SRAMs under Process Variations beyond 22nm
42: (2015)
Implementation of a Real-Time Spectrum Analyzer on FPGA Platforms
43: (2015)
Implementation of a Real-Time Spectrum Analyzer on FPGA Platforms
44: (2015)
Real-Time Low-Complexity Automatic Modulation Classifier for Pulsed Radar Signals
45: (2015)
Real-Time Low-Complexity Automatic Modulation Classifier for Pulsed Radar Signals
46: (2015)
2.64 pJ Reference-Free Power Supply Monitor with a Wide Temperature Range
47: (2016)
A Performance Study of CUDA UVM versus Manual Optimizations in a Real-World Setup: Application to a Monte Carlo Wave-Particle Event-Based Interaction Model
48: (2016)
A Performance Study of CUDA UVM versus Manual Optimizations in a Real-World Setup: Application to a Monte Carlo Wave-Particle Event-Based Interaction Model
49: (2016)
A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices
50: (2016)
Calibration-free 1052 mu m(2) Power Supply Monitor
51: (2016)
Characterization of Analog Modules: Reliability Analyses of Radiation, Temperature and Variations Effects
52: (2016)
Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges.
53: (2016)
Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges.
54: (2016)
Reliable Design Methodology: The Combined Effect of Radiation, Variability and Temperature
55: (2016)
SPICE Compact Modeling of Bipolar/Unipolar Memristor Switching Governed by Electrical Thresholds
56: (2016)
Taxonomy of Power Supply Monitors and Integration Challenges
57: (2017)
A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices
58: (2017)
Democratizing science with the aid of parametric design and additive manufacturing: Design and fabrication of a versatile and low-cost optical instrument for scattering measurement
59: (2017)
On the Design and Analysis of Reliable RRAM-CMOS Hybrid Circuits
60: (2017)
On the Design and Analysis of Reliable RRAM-CMOS Hybrid Circuits
61: (2017)
Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges
62: (2018)
A temperature variation tolerant CMOS-only voltage reference for RFID applications
63: (2018)
Auto-Erasable RRAM Architecture Secured Against Physical and Firmware Attacks
64: (2018)
Guest Editorial: Special Section on Fast Fourier Transform (FFT) Hardware Implementations
65: (2018)
Performance-oriented Implementation of Hilbert Filters on FPGAs
66: (2018)
Self-controlled multilevel writing architecture for fast training in neuromorphic RRAM applications
67: (2019)
A low power RFID based energy harvesting temperature resilient CMOS-only reference voltage
68: (2019)
A 365mV, 13nW CMOS-only energy harvested reference voltage for RFID applications in 40nm technology
69: (2019)
Simple method to generate calibrated synthetic smoke-like atmospheres at microscopic scale
70: (2019)
Temperature-aware writing architecture for multilevel memristive cells
4 Capítulos de libros
1: (2007)
Joint Source-Channel Decoding ASIP Architecture for Sensor Networks
2: (2009)
SoC Communication Architectures: From Interconnection Buses to Packet-Switched NoCs
3: (2012)
Temperature Monitoring Issues in Nanometer CMOS Integrated Circuits
4: (2012)
Temperature Monitoring Issues in Nanometer CMOS Integrated Circuits.
6 Conferencias invitadas en congresos
1: (2010)
System-on-Chip monitoring networks targeting nanometer technologies
2: (2012)
Monitoring: a lifeboat in a varying environment
3: (2013)
DCIS 2013 Special Session. Variability and Reliability
4: (2017)
Robust design based on variability monitoring
5: (2018)
Bringing emerging technologies into the real world
6: (2019)
A 365mV, 13nW CMOS-only energy harvested reference voltage for RFID applications in 40nm technology
1 Cursos, seminarios y tutoriales
1: (2015)
On-chip PVT Variation Monitoring
55 Ponencia en Congresos
1: (2007)
Exploring Temperature-Aware Design of Memory Architectures in VLIW Systems
2: (2007)
FPGA Gaussian Random Number Generator Based on Quintic Hermite Interpolation Inversion
3: (2007)
Leakage-based On-Chip Thermal Sensor for CMOS Technology
4: (2007)
Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors
5: (2007)
Thermal Analysis of the Shared Register File in VLIW Architectures.
6: (2008)
A Novel Small Low-Power Interface for On-Chip Thermal Sensors
7: (2008)
A Web-based Environment Providing Remote Access to FPGA Platforms for Teaching Digital Hardware Design
8: (2008)
An FPGA Implementation of the Powering Function with Single Precision Floating-Point Arithm
9: (2008)
An FPGA Run-Time Parameterisable Log-Normal Random Number Generator
10: (2008)
Docencia Semipresencial en Laboratorios Docentes para Diseño de Hardware Digital en la ETSIT-UPM
11: (2008)
Experimental Methodology for Power Characterization of FPGAs
12: (2008)
Variance reduction techniques for Monte Carlo simulations. A parameterizable FPGA approach
13: (2009)
Development of a standard single floating-point library and its encapsulation for reuse
14: (2009)
Exploring Performance-Power Trade-offs for Look-Up Tables in SRAM-based FPGAs
15: (2009)
Providing Self-learning to Students of Highly Attended Electronics Courses through the Remote Access to a Microelectronics Laboratory
16: (2010)
Design of an Efficient Interconnection Network of Temperature Sensors
17: (2010)
On the Hardware Implementation of Triangle Traversal Algorithms for Graphics Processing
18: (2011)
Area-delay Trade-offs of Texture Decompressors for a Graphics Processing Unit
19: (2011)
Area-Efficient Linear Regression Architecture for Real-Time Signal Processing on FPGAs
20: (2011)
Assesing Self-Learning Electronics through the Support of Remote Labs
21: (2011)
Cycle-Accurate Configuration Layer Model for Xilinx Virtex FPGAs
22: (2011)
FPGA Acceleration of Monte Carlo-based Financial Simulation: Design Challenges and Lessons Learnt
23: (2011)
FPGA acceleration of Monte Carlo-based financial simulation: Design challenges and lessons learnt
24: (2011)
ON-CHIP MONITORING: A LIGHT-WEIGHT INTERCONNECTION NETWORK APPROACH
25: (2011)
On-chip Monitoring: A Light-Weight Interconnection Network Approach
26: (2011)
Real Time FPGA Implementation of an Modulation Classifier for Electronic Warfare Applications
27: (2011)
Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs
28: (2012)
A CAD framework for the characterization and use of memristor models
29: (2012)
A Monitoring Infrastructure for FPGA Self-Awareness and Dynamic Adaptation
30: (2012)
Design and Implementation of Floating-Point FFT Architectures for FPGA Devices
31: (2012)
Hardware Reuse Improvement through the Domain Specific Language dHDL
32: (2012)
Hardware Reuse Improvement through the Domain Specific Language dHDL.
33: (2012)
Improving Hardware Reuse through XML-based Interface Encapsulation
34: (2012)
Temperature Sensor Placement Including Routing Overhead and Sampling Inaccuracies
35: (2013)
A Low-Area Reference-Free Power Supply Sensor
36: (2013)
Improvement of Radar Capabilities by Reconfigurable Digital Signal Processing
37: (2014)
A built-in CMOS Total Ionization Dose smart sensor
38: (2014)
A tool for the automatic analysis of single events effects on electronic circuits
39: (2014)
Four-injector variability modeling of FinFET predictive technology models
40: (2014)
Implementation tradeoffs of triangle traversal algorithms for graphics processing
41: (2014)
Real-time radar pulse parameter extractor
42: (2015)
A Dual-Layer Fault Manager for Systems based on Xilinx Virtex FPGAs
43: (2015)
A Thermal Adaptive Scheme for Reliable Write Operation on RRAM Based Architectures
44: (2015)
Evolution of Radiation-Induced Soft Errors in FinFET SRAMs under Process Variations beyond 22nm
45: (2015)
Evolution of Radiation-Induced Soft Errors in FinFET SRAMs under Process Variations beyond 22nm
46: (2016)
A temperature-independent PUF with a configurable duty cycle of CMOS ring oscillators
47: (2016)
Calibration-free 1052 µm2 power supply monitor
48: (2016)
Characterization of analog modules: Reliability analyses of radiation, temperature and variations effects
49: (2016)
Reliable Design Methodology: The Combined Effect of Radiation, Variability and Temperature
50: (2016)
Taxonomy of Power Supply Monitors and Integration Challenges
51: (2017)
Advanced integration of variability and degradation in RRAM SPICE compact models
52: (2017)
CAS-T Lecture: Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges
53: (2017)
CAS-T Lecture: SPICE Compact Modeling of Bipolar/Unipolar Memristor Switching Governed by Electrical Thresholds
54: (2018)
Performance-oriented Implementation of Hilbert Filters on FPGAs
55: (2019)
Temperature-aware writing architecture for multilevel memristive cells
Explotación de Resultados y Transferencia de Tecnología
1 Creación de empresas
1: (2010)
SPEEDUP Systems España, Sociedad Limitada
4 Patentes
1: (2007)
Aparato para la medida de temperatura y corriente de fugas en un chip
2: (2008)
Aparato para la medida de temperatura y corriente de fugas en un chip
3: (2008)
Procedimiento y arquitectura electrónica para la detección SOVA óptima basado en el rastreo de puntos de fusión
4: (2009)
Aparato para la medida de temperatura y corriente de fugas en un chip
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S2i 2021 Observatorio de investigación @ UPM con la colaboración del Consejo Social UPM
Cofinanciación del MINECO en el marco del Programa INNPACTO (IPT-020000-2010-22)
