Descripción
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Mersenne Twister (MT) uniform random number generators are key cores for hardware acceleration of Monte Carlo simulations. In this work, two different architectures are studied: besides the classical table-based architecture, a different architecture based on a circular buffer and especially targeting FPGAs is proposed. A 30% performance improvement has been obtained when compared to the fastest previous work. The applicability of the proposed MT architectures has been proven in a high performance Gaussian RNG. | |
Internacional
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Si |
JCR del ISI
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Si |
Título de la revista
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Journal of Signal Processing Systems |
ISSN
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1939-8018 |
Factor de impacto JCR
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Información de impacto
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Volumen
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71 |
DOI
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dx.doi.org/10.1007/s11265-012-0684-4 |
Número de revista
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2 |
Desde la página
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105 |
Hasta la página
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109 |
Mes
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MAYO |
Ranking
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