Observatorio de I+D+i UPM

Memorias de investigación
Thesis:
Aportaciones metodológicas para el diseño de descodificadores de vídeo de última generación sobre plataformas Multi-DSP
Year:2017
Research Areas
  • Electronic technology and of the communications
Information
Abstract
This Ph.D. work is integrated into the digital video coding and decoding research lines of the Electronic and Microelectronic Research Group (GDEM), Universidad Politécnica de Madrid. Previous dissertations were mainly focused in the implementation of video codecs over specific hardware architectures, specifically in performance optimization and development time reduction. However, these proposals centered their attention on single-core architectures. Nowadays, the increase in the algorithmic complexity of new coding standards, together with the massive adoption of multicore processors, is pushing towards the conception of new design methodologies that improve designer?s efficiency. Succeeding in this goal, would help in providing more flexible solutions for the implementation of new video decoders over multicore platforms. During the last decade, the use of a large range of multicore architectures in multimedia devices has become widespread. The Multicore Digital Signal Processors (Multi-DSP) are specially designed to improve the performance of algorithms like those used on video decoders. However, programming this kind of processors has posed two main difficulties. On one side, the reference code of video codecs is typically optimized for other, more generic platforms, so it needs to be efficiently migrated, which involves long development times. Besides, software support for these platforms is reduced, as proven by the fact, among others, that no operating system is usually provided to both, help the development tasks and support the applications to take advantage of the hardware resources. Therefore, the proposal of new methodological solutions becomes necessary to take advantage of the Multi-DSP benefits while reducing the time to market. The main objective of this thesis is the development of a design methodology that allows the implementation of state-of-the-art video decoders for Multi-DSP platforms. First, a detailed study about the state-of-the-art on video codecs has been done. In this regard, the High Efficiency Video Coding (HEVC) standard is the newest one and it has been recently standardized. Complementary to the coding tools, the Reconfigurable Video Coding (RVC) standard allows the development of video codecs from a high-level description based on the paradigm of dataflow models of computation. The use of RVC-based solutions introduces flexibility, modularity and reusability of video codecs implementations. Also, it eases the runtime management and the parallel execution of the different actor, i.e., functional units, of the dataflow graph on the available computational resources. Secondly, a review of video coding implementation technologies has been done too, mainly focused on DSPs and GPPs platforms. Besides, an analysis of the state-of- the-art on multicore programming methodologies has been carried out. As a result, it turned that none of them had addressed the main target of this work: to contribute to improve the design phase for Multi-DSP technologies. Although the proposal contained herein is highly focused on the development of video codecs, as it is based on the RVC standard, it is general enough to be useful with other types of architectures and applications. During the development of this work, it has been necessary to evaluate, select and use different tools and technologies in order to develop video decoders for Multi- DSP platforms under the analyzed conditions. These tools support key aspects such as code parallelization, algorithm optimization features (for the decoders), as well as automatic source code generation. Finally, the proposed design methodology is based on the experience obtained during the practical implementation of different video decoders over Multi-DSP platforms. The methodology and tools developed in this work have been incorporated into Open RVC CAL Compiler (Orcc), an open source tool that allows the automatic source code generation from RVC-based models.
International
Si
Type
Doctoral
Mark Rating
Sobresaliente cum laude
Date
28/06/2017
Participants
  • Director: Fernando Pescador Del Oso (UPM)
  • Director: Matias Javier Garrido Gonzalez (UPM)
  • Autor: Miguel Chavarrias Lapastora (UPM)
Research Group, Departaments and Institutes related
  • Creador: Grupo de Investigación: Grupo de Diseño Electrónico y Microelectrónico
  • Centro o Instituto I+D+i: Centro de Investigación en Tecnologías del Software y Sistemas Multimedia para la Sostenibilidad (CITSEM)
  • Departamento: Ingeniería Telemática y Electrónica
S2i 2019 Observatorio de investigación @ UPM con la colaboración del Consejo Social UPM
Cofinanciación del MINECO en el marco del Programa INNCIDE 2011 (OTR-2011-0236)
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