Observatorio de I+D+i UPM

Memorias de investigación
Research Publications in journals:
1/f Electrical Noise in Planar Resistors: The Joint Effect of a Backgating Noise and an Instrumental Disturbance
Year:2008
Research Areas
  • Electronics engineering
Information
Abstract
Any planar resistor (channel) close to a conducting layer left floating (gate) forms a capacitor C whose thermal voltage noise (kT/C noise) has a backgating effect on the sheet resistance of the channel that is a powerful source of 1/f resistance noise in planar resistors and, hence, in planar devices. This 1/f spectrum is created by the bias voltage VDS applied to the resistor, which is a disturbance that takes it out of thermal equilibrium and changes the resistance noise that existed in the unbiased device. This theory, which gives the first electrical explanation for 1/f electrical noise, not only gives a theoretical basis for the Hooge’s formula but also allows the design of proper shields to reduce 1/f noise. Index
International
Si
JCR
Si
Title
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT
ISBN
0018-9456
Impact factor JCR
0,832
Impact info
Volume
57
10.1109
Journal number
3
From page
509
To page
517
Month
MARZO
Ranking
Participants
  • Autor: Jose Ignacio Izpura Torres (UPM)
Research Group, Departaments and Institutes related
  • Creador: Grupo de Investigación: Microsistemas y Materiales Electrónicos
  • Departamento: Ingeniería Electrónica
S2i 2019 Observatorio de investigación @ UPM con la colaboración del Consejo Social UPM
Cofinanciación del MINECO en el marco del Programa INNCIDE 2011 (OTR-2011-0236)
Cofinanciación del MINECO en el marco del Programa INNPACTO (IPT-020000-2010-22)