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Descripción
Mersenne Twister (MT) uniform random number generators are key cores for hardware acceleration of Monte Carlo simulations. In this work, two different architectures are studied: besides the classical table-based architecture, a different architecture based on a circular buffer and especially targeting FPGAs is proposed. A 30% performance improvement has been obtained when compared to the fastest previous work. The applicability of the proposed MT architectures has been proven in a high performance Gaussian RNG.
Internacional	Si
JCR del ISI	Si
Título de la revista	Journal of Signal Processing Systems
ISSN	1939-8018
Factor de impacto JCR
Información de impacto
Volumen	71
DOI	dx.doi.org/10.1007/s11265-012-0684-4
Número de revista	2
Desde la página	105
Hasta la página	109
Mes	MAYO
Ranking

Esta actividad pertenece a memorias de investigación

• Autor: M. Luisa Lopez Vallejo (UPM)

• Creador: Grupo de Investigación: Laboratorio de Sistemas Integrados (LSI)